Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: Writing Scheme of Cache Memory - Computer Science Engineering (CSE) MCQ

Test: Writing Scheme of Cache Memory - Computer Science Engineering (CSE) MCQ


Test Description

15 Questions MCQ Test - Test: Writing Scheme of Cache Memory

Test: Writing Scheme of Cache Memory for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Writing Scheme of Cache Memory questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Writing Scheme of Cache Memory MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Writing Scheme of Cache Memory below.
Solutions of Test: Writing Scheme of Cache Memory questions in English are available as part of our course for Computer Science Engineering (CSE) & Test: Writing Scheme of Cache Memory solutions in Hindi for Computer Science Engineering (CSE) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Writing Scheme of Cache Memory | 15 questions in 25 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Writing Scheme of Cache Memory - Question 1

Which of the following is the biggest challenge in the cache memory design?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 1

Explanation: The coherency is a major challenge in designing the cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.

Test: Writing Scheme of Cache Memory - Question 2

What arises when a copy of data is held both in the cache and in the main memory?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 2

Explanation: The stale data arises when the copy is held both in the cache memory and in the main memory. If either copy is modified, the other data become stale and the system coherency can be destroyed.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: Writing Scheme of Cache Memory - Question 3

 In which writing scheme does all the data writes go through to main memory and update the system and cache?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 3

Explanation: There are different writing scheme in the cache memory which increases the cache efficiency and one such is the write-through in which all the data go to the main memory and can update the system as well as the cache.

Test: Writing Scheme of Cache Memory - Question 4

 In which writing scheme does the cache is updated but main memory is not updated?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 4

Explanation: The cache write-back mechanism needs a bus snooping system for the coherency. In this write-back scheme, the cache is updated first and the main memory is not updated.

Test: Writing Scheme of Cache Memory - Question 5

In which writing scheme does the cache is not updated?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 5

Explanation: The no caching write cycle does not update the cache but the data is written to the cache. If the previous data had cached, that entry is invalid and will not use. This makes the processor fetch data directly from the main memory.

Test: Writing Scheme of Cache Memory - Question 6

Which writing mechanism forms the backbone of the bus snooping mechanism?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 6

Explanation: The no caching of write cycle seems to be wasteful because it does not update the cache, and if any previous data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this writing scheme forms the backbone of the bus snooping system for the coherency issue.

Test: Writing Scheme of Cache Memory - Question 7

What is the main idea of the writing scheme in the cache memory?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 7

Explanation: There are four main writing scheme in the cache memory which is, write-through, write-back, no caching of the write cycle and write buffer. All these writing schemes are designed for bus snooping which can reduce the coherency.

Test: Writing Scheme of Cache Memory - Question 8

 In which scheme does the data write via a buffer to the main memory?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 8

Explanation: The write-buffer is slightly similar to the write-through mechanism in which data is written to the main memory but in write buffer mechanism data writes to the main memory via a buffer.

Test: Writing Scheme of Cache Memory - Question 9

Which of the following can allocate entries in the cache for any data that is written out?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 9

Explanation: A write-allocate cache allocates the entries in the cache for any data that is written out. If the data is transferred to the external memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is advantageous.

Test: Writing Scheme of Cache Memory - Question 10

Which of the following uses a bus snooping mechanism?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 10

Explanation: The bus snooping mechanism uses a combination of cache tag status, write policies and bus monitoring to ensure coherency. MC88100 or MC88200 uses bus snooping mechanism.

Test: Writing Scheme of Cache Memory - Question 11

What lead to the development of MESI and MEI protocol?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 11

Explanation: The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 have MESI protocol and MC68040 uses an MEI protocol.

Test: Writing Scheme of Cache Memory - Question 12

Which of the following is also known as Illinois protocol?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 12

Explanation: The MESI protocol is also known as Illinois protocol because of its formation at the University of Illinois.

Test: Writing Scheme of Cache Memory - Question 13

What does MESI stand for?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 13

Explanation: The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In MESI protocol, multiple processors can cache shared data.

Test: Writing Scheme of Cache Memory - Question 14

What does MEI stand for?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 14

Explanation: MEI protocol is less complex and is easy to implement. It does not allow shared state for the cache.

Test: Writing Scheme of Cache Memory - Question 15

 Which protocol does MPC601 use?

Detailed Solution for Test: Writing Scheme of Cache Memory - Question 15

Explanation: MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor specific. So different processors have different cache coherency implementations.

Information about Test: Writing Scheme of Cache Memory Page
In this test you can find the Exam questions for Test: Writing Scheme of Cache Memory solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Writing Scheme of Cache Memory, EduRev gives you an ample number of Online tests for practice

Top Courses for Computer Science Engineering (CSE)

Download as PDF

Top Courses for Computer Science Engineering (CSE)