Test: Burst Interfaces - Computer Science Engineering (CSE) MCQ

Explanation: The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.

Explanation: The burst interfaces uses the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.

Explanation: The speed of the memory can be improved by the page mode or the static column memory which offer a faster access in a single cycle.

Explanation: The burst interfaces reduces the clock cycles. For fetching four words with a three clock memory, it will take 12 clock cycle but in the burst interface, it will only take five clocks to access the data.

Explanation: In the burst interface, the first access of the memory address requires two clock cycles and single cycle for the remaining memory address.

Explanation: In the burst interface, the address is supplied only for the first access and not for the remaining accesses. An external logic is required for the additional addresses for the memory interface.

Explanation: The burst interfacing uses an unequal timing. It takes two clocks for the first access and only one for the remaining accesses which make it an unequal timing.

Explanation: The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.

Explanation: The burst interface is associated with the static RAM.

Explanation: MC68040 is developed by the Motorola which uses a wrap around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap around burst. US 5729504 A uses a linear burst fill.