Test: UART: Embedded Systems I/O - Computer Science Engineering (CSE) MCQ

Explanation: The UART or universal asynchronous receiver transmitter is used for the data transmission at a predefined speed or baud rate.

Explanation: The data can be detected by the local clock reference which is generated from the baud rate generator.

Explanation: The TXD signal goes to logic one, when no data is transmitted. When data transmits, it sets to logic zero.

Explanation: The timing is defined by the baud rate in which both the transmitter and receiver are used. The baud rate is supplied by the counter or an external timer called baud rate generator which generate a clock signal.

Explanation: The baud rate is supplied by the counter or an external timer called baud rate generator which generate a clock signal.

Explanation: The Intel 8253, 8254 and 8259 are timers whereas Intel 8250 is a UART which is commonly used.

Explanation: The Intel 8250 is replaced by the 16450 and 16550 which are developed by the National Semiconductors. 16450 is a chip which can combines all the PC’s input output devices into a single piece of silicon.

Explanation: The ADS is address strobe signal and is working as active low in 8250 UART. The ADS signal is used to latch the address and chip select signals while a processor access.

Explanation: The BAUDOUT signal is active low whereas DDIS, INTR and MR are active high in the 8250 UART. BAUDOUT is the clock signal from the transmitter part of the UART. DDIS signal goes low when the CPU is reading data from the UART. INTR is the interrupt pin. MR is the master reset pin.

Explanation: DDIS signal goes low when the CPU is reading data from the UART and it also controls the bus arbitration logic.

Explanation: MR is the master reset pin which helps to reset the device and restore the internal registers.

Explanation: RCLK provides an input clock for the receiver part of the UART. RD is the read signal. MR is the master reset pin and DDIS is used to control bus arbitration logic.

Explanation: There are two general purpose I/O pin OUT1 and OUT2. OUT1 is set by the programming bit 2 of the MCR to a ‘1’ whereas OUT2 is set by the programming bit 3 of the MCR to ‘1’. These are active low pins in 8250.

Explanation: RD and WR signals are indicating the type of access that the CPU needs to perform, that is, whether it is a read cycle or write cycle.

Explanation: The RXRDY and TXRDY are two active low pins which are used for additional DMA control. It can be used for DMA transfers to and from the read and write buffers.

Explanation: The CPU is responsible for moving data to and from the UART in the IBM PC, therefore it does not have TXRDY and RXRDY pins which are used for DMA accessing.

Explanation: The XIN and XOUT pins are used to connect an external crystal. These pins can also connect external clock.

Explanation: The MC68681 is a standard UART developed by Motorola. It has been used in many MC680 by 0 designs.

Explanation: The largest buffer of 16 bytes is available on 16550 UART which is used for high speed data communications.

Explanation: The MC68681 is a standard UART developed by Motorola. It possess a quadruple buffered receiver and a double buffered transmitter.