Test: Formal Verification, Risk & Dependability Analysis - Computer Science Engineering (CSE) MCQ

Explanation: Many formal verification techniques are used and these are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The FOL is the abbreviated form of the first order logic which includes the quantification.

Explanation: The formal verification techniques are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The HOL is the abbreviation of the higher order logic in which the proofs are automated and manually done with some proof support.

Explanation: The binary decision diagram is a kind of data structure which is used to represent the Boolean function.

Explanation: The propositional logic technique is having the boolean formulas and the boolean function. The tools used in propositional logic is the tautology checker or the equivalence checker which in turn uses the binary decision diagrams which is also known as BDD.

Explanation: The propositional logic technique consists of the boolean formulas and the boolean function. The tools used in this type of logic is the tautology checker or the equivalence checker which in turn uses the BDD or the binary decision diagrams.

Explanation: The model checking was developed using the binary decision diagram and the BDD and it was possible to locate errors in the specification of the future bus protocol.

Explanation: The EMC-system is developed by Clark and it describes the CTL formulas, which is the computational tree logics.

Explanation: The EMC-system is a popular system for model checking which is developed by Clark that describes the CTL formulas, which is also known as computational tree logics. The CTL consist of two parts, a path quantifier, and a state quantifier.

Explanation: The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with a damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.

Explanation: The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with a damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.

Explanation: The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation, if several events cause hazards.

Explanation: The FTA is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous.

Explanation: The fault tree analysis is done graphically by using gates. The main gates used are AND gates and OR gates. The AND gates are used in the graphical representation, if several events cause hazards.

Explanation: The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.

Explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.