Pass Transistor Logic Circuits - I - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)

hello and welcome to today's lecture on
pass-transistor logic circuits in the
last couple of lectures we have
discussed how boolean functions can be
realized by using static CMOS circuits
and dynamic CMOS circuits those are
essentially known as gate logic because
inputs are applied to the gate and you
take the output from source or drain of
the canisters and earlier we have
discussed about the use of transistors
as a switch today we shall discuss how
you can realize boolean functions using
transistors as a switch this is
typically known as past install logic
circuits so here is the agenda of
today's lecture after giving a brief
brief introduction I shall discuss about
pass transistor logic circuit design
rules then discuss about their
advantages and disadvantages
and also we shall discuss how various
decide this advantages can be overcome
so let us start with a brief
introduction which which is essentially
a recapitulation of what we have
discussed earlier we know that an ideal
switch have zero resistance and that
means whenever you apply an input it
will reach unattenuated say suppose this
is a switch whatever is inside let us
forget so let me represent it by this a
switch and you are applying an input V
in and you are getting an output
ideally V in should be equal to V out
when switch is on
and whenever switches off then we in
should not be via via what irrespective
of V in V out should be equal to zero
zero volt or zero so when switches off
so this is the ideal characteristics as
you know and we have we also know that a
relay which is a electromechanical
device can act as a ideal switch as an
ideal switch
however it's switch it is very slow so
switching characteristics is not except
acceptable in present-day circuits there
was a classical book still it is it may
not be available now written by Calvin
who provide who provided a chapter where
you can realize circuits using relay
logic that means using relays as the
building blocks boolean functions can be
realized
so the Allah is relay logic is provided
and in case of relay presence of input
that means whenever you apply say
suppose this is the relay and if you
apply an input which is equal to say hi
that means if input is available then
you get if the switch is closed you get
V whatever is V in you get as V out that
means V out is equal to V in respective
up high or low whenever V in is not
present that means there is no input
applied to it then V out is equal to
zero that means in case of Radiologic
absence of input provides a zero output
that means that absol
of import is treated as low input and at
the output you get zero whenever the
switch is closed so however as we shall
see past tense the logic is different
from relay logic because we cannot
really use the techniques that has been
used to realize a boolean functions by
using relay logic to pass transistor
logic and in what way they differ we
shall discuss in detail but before that
as I told we shall be using MOS
transistors as switch very quickly
recapitulate us recapitulate what we
discussed earlier we know that an N Mo's
transistor as a switch can be used and
when the gate voltage is zero
then the transistor is off and when gate
voltage is VDD the transistor is on and
we also know that a low level signal can
be fast through the switch without any
degradation as it is shown here if zero
volt is applied you get zero volt and a
high level signal cannot be passed
without any degradation as we know at
the output you will get V DD minus VT n
where VT n is the threshold voltage of
the N Mo's transistors so this is the
characteristics of a n MOS transistor as
a switch and similarly if we use a P
Mo's transistor as a switch when vgs is
equal to VDD the transistor is off if
you apply VDD here the 10 stirrer is off
and when vgs is equal to zero volt the
transistor is on and as you know a low
level signal cannot be passed without
any degradation because you will get a
voltage which is equal to VT P I mean
absolute value of VT P apply a hold VDD
here that means if if you apply a 0 volt
here you will not get 0 here but you
will get a minimum voltage of VT P
because this transistor will turn off
when the voltage gets discharged beyond
VT P point
then high level say however a high level
signal can be passed without any
degradation as we know so if we apply
VDD you get VDD
with a 0 in the z-row applied to the
gate so minimum voltage that it can pass
is VT feed
we can make a conclusion from this and
we can combine the advantages of n Mo's
and P Mo's transistors to realize the
transmission gate where both 0 and high
level low and high level can pass
without any degradation and where we use
to pass transistors two transistors one
in Mo's and one P MOS in parallel
however this will require control
signals you can see complimentary
control signals that means if this is
the switch this is the transmission gate
then if you apply some MSA control
signal if you apply here this is your V
in and this is V out that means if you
apply zero here you have to apply one
that means you may have to use an
inverter and if this is the control
signal coming from some other source to
be able to apply to the two gates so you
require either complementary signals or
you have to use an inverter to
compliment the control signal to have to
be applied to the other input so the
number of transistors that you really
require in realizing a switch is quite
large
in case of transmission gate used as a
switch and that so we can say that we
can from this we can our observation is
MOS transistors can be used as switches
with that with some limitations
transmission gates provides near optimal
switch in case of transmission gate as
we have seen two parallel transistor
supply current to the load and
realization of boolean functions using
transmission gate requests larger area
because as we have seen you not only
require two transistors to realize
switch to generate control signals you
may require another inverter so that is
the reason why instead of using
transmission gate n MOS transistors are
commonly used to realize pass transistor
logic circuits that means in switch
logic whenever you realize boolean
function
using transistor and switch usually a
and usually an n MOS transistor is used
usually switch instead of using
transmission gate
although transmitted gate is closer to
an ideal switch okay with this brief
introduction let us now see in what way
I mean how we can realize pass
transistor logic circuits first let us
discuss about some logic design rules as
we know so whenever you are using an
Mo's transistor as a switch then if we
apply VDD here let us assume the
transistor is on so if we apply VDD here
the maximum voltage that you can use
here we did is VDD minus VT n suppose
VDD is equal to 5 volt and V TN is
called to say point to VDD let's assume
it is 1 volt then what will happen if
this is equal to 5 volt here you will
get 4 volt now if this is used as a
control signal to another stage what
will happen here if we apply VDD is
equal to 5 volt here we shall get VDD we
shall get 3 volt the reason is you see
here we are applying for volts so that
means this transistor will turn off when
this voltage will charge 2 3 4 level in
a similar way suppose this we apply is a
control signal to another stage then
what will happen
and if VDD will get degraded too much
and here we shall get 3 volt that means
if the output of a pass transistor logic
I mean n MOS Tunstall logy is a switch
if is that if it is applied as a input
to a gate to the next stage then the
voltage further degrades
that means so here it will be to hold
sorry so four three and two so to hold
so it is getting degraded because if it
is 3 volt here this voltage this point
cannot charge beyond to hold so you can
see there is severe degradation and it
may so happen that the next stage may
not treat this see if we apply to some
gate logic circuit then it may not be
treated as a high level moreover if it
is driving to say suppose if it is
driving to a to an inverter then what
will happen they drive that will that it
will provide to the to this n MOS
transistor will be quite low and as a
consequence the because the drive even
if it is treated as a high level the
drive to this transistor will be quite
low when the input is high and as a
consequence this will affect the
switching characteristic of the device
that means with 2 volt as the input
voltage to the gate as you know the
saturation current is equal to VDD minus
VT n Square proportional to that and as
a consequence the current will be
significantly less and as a consequence
the switching characteristic will be
very inferior so from this we can say
that one first design rule that you can
you should use is one must not drive so
this is the design rule one must not
drive the output
of a past instead of a past and Easter
one must not drive the output person as
input rather control input should say
control input control input to the next
stage that means what we shall do we
shall never use this that means this
signal we shall never use it at control
signal to the next stage
so either we shall put an inverter here
buffer to to to restore the level and
then we shall apply to the next stage so
you can this is the first rule that you
have to follow while realizing circuits
using N Mo's as switch okay this is the
first rule that you have to follow then
the second rule we shall come from this
observation suppose we have to realize a
function f is equal to a plus B Square C
conventionally if we realize it by a
relay logic the representation is like
this this is controlled by a and this is
controlled by B - and this is controlled
by another switch C and we get the
output from here that means if we apply
an input here and through these two
switches that means when a is 1 this
switch is closed so signal will pass
through it and when VDS is equal to 1
and C is equal to 1 D the signal will
pass through it and this is how it will
work and this is the circuit this is the
realization to to realize this function
f2 for of course here you will apply VDD
or I mean in terms of our most circuits
so that means if we apply here VDD and
then
use these three switches and we shall
realize this function f so as we can see
whenever this switches are off we shall
be getting zero volt either is I mean
either B's of or series of or a V dash
and CS all are one in that case all are
zero in that case also this switch will
go up that means if there is no path
then output will be zero so this is how
you can realize by using relay logic now
suppose we use the same approach to
realize the function by using pass
transistor let's assume we use three n
MOS transistors three n MOS transistors
here we apply a here we apply B dash
here we apply C and following the
convention of relay logic here we apply
VDD and here we are expecting the output
V out question is will VI would be equal
to how to be V out will it be equal to F
that is the question will it be equal to
F the function that is that is shown
here what is the answer unfortunately if
we if we realize the function based on
relay logic it will not produce correct
output why it will not produce correct
output the reason for that is you see it
will produce correct output so far as
the high output level is concerned that
means whenever this switch is closed it
will produce me out of course it will
not produce me out but V out minus VDD
as you let us assume we shall take it as
a high level but let's assume the case
whenever so that means whenever the
output is say a B C so when the input is
1 0 0 then it will produce 1 or whenever
it will the output is say 0 0 1 then you
can produce 1
0:01 BDS is equal to so this path is
closed it will produce one that means
this is 1 this is 1 then also it will
produce 1 but what about the case say
whenever we apply say 0 0 0 all are 0 or
let's as you whenever the input says 0 1
0 I am NOT writing all possible
combinations so for these imports it is
supposed to produce 0 let's assume after
applying any one of these inputs we
apply 0 0 0 then what will happen
shall we get 0 at the output the answer
is no why the reason for that is now
whenever after applying any one of the
inputs whenever we apply either 0 0 0 or
0 1 0 what will happen there is no path
to VDD yes this is off this is off this
is I mean I mean whenever it is 0 0 0 9
that this part not this part is closed
so you are supposed to get a 0 here but
unfortunately capacitor is now charged
to VDD because of the previous input so
as you know it retains the charge at the
output and as a consequence it will
continue to produce hi if this input is
applied after this or this input is
applied after any one of these 2 input
that means after producing output
I mean producing hi at the output if any
input combination is applied for which
we are supposed to get 0 it will not
produce 0 in that case what is the
solution solution is that we have to
realize the circuit in such a way that
it will provide path for 0 also that
means for 1 it is getting path through
this that means to charge this capacitor
to high level the path is this I mean
when a is 1 this is the path when B - C
is 1 this is the path but what about
when F is supposed to be 0 so we have to
provide a path for discharging the
capacitor how can you provide that that
means we have to
we have to put additional path such that
the output is I mean it should it should
produce zero when by discharging the
capacitor when the input combination is
input combination is such output is zero
so what we can do we can provide this
kind of thing say a des is connected and
we provide zero here zero means zero
volt now as you can see if we apply any
other input combinations then you will
see that it will provide it will for for
this input or this input it will produce
a zero output because this this switch
you will now close and discharge the
capacitor to zero level that means so
what is the design rule - what is our
design rule to design rule - is it is
essential to provide both charging and
discharging path
for the load capacitance that means when
the output is supposed to be zero there
should be a discharge path of the
capacitor when the output is supposed to
be one there will be charging path so
this is how we have to use realize the
circuit by using pass transistor logic
so this is the second rule that we have
to follow while realizing circuits by
using pass transistor logic what about
the third rule is there any other
problem here actually another rule is
there design rule three designs rule
three comes from say suppose this is a
pass transistor not Network first
transistor Network
where you will be applying zero volt and
VDD as input and of course those various
fungus inputs you will apply as control
signals and here it will produce output
where let's assume we have a load
capacitance CL now it may so happen that
the output there is a path directly to
the zero to to this zero volt and also
there is a path directly to the VDD that
means both paths are realized
advertently or inadvertently it may so
happen because of some mistake in the
design what has happened there is path
either both from zero from the low level
as well as from high level this will
lead to an output which is undefined
that means it will depend on the you
know that it will act they will act as a
kind of potential divider and you will
get output which is neither 0 nor 1 so
you will get some undefined output so
what is the your design rule to so you
have to avoid
simultaneous path
simultaneous path to zero and VDD how
later on we shall see so this is your
design rule we followed and if we
realize circuits by using three design
rules then it will reproduce character
output and you can realize any general
boolean function later on we shall
discuss in detail how we can realize
general boolean function using pass
transistor logic but before that let us
look at the advantages and disadvantages
first advantage is ratio less why it is
ratio less it is ratio less because the
output is not dependent on the size of
the NMOS or PMO's transistors so unlike
your gate logic realized by using n MOS
circuit or pseudo n MOS circuit where
the W by L ratio of the pull-up -
pulldown device affects the output
voltage at low level and we have to
maintain some ratios such that you get
proper low level output here of course
that is not true that means it is ratio
less what is the impact of this the
impact is you can realize circuits with
transistors of minimum dimension that
means two lambda by 2 lambda lambda is
the minimum feature size for a
particular process technology you can
realize circuits by using transistors of
minimum dimension that means 2 lambda by
2 lambda both for N Mo's and P Mo's
transistors if you require so in in this
base in this case however you are really
you realizing using only n Mo's
transistors so all of them will be up
smaller than smallest dimension small
diamond smallest dimension means 2
lambda by 2 lambda and obviously it will
have a smaller area this will lead to
smaller area of realization this is the
outcome of this second is lower area due
to smaller number of transistors there
is another important feature of us
transistor logic circuit is that you can
realize boolean functions with smaller
number of transistors then this tears
are of smaller size and also you will
require smaller number of transistors
later on we shall discuss about the
realization of some benchmark circuits a
full adder on other things you will see
the pass transistor logic realization
will require smaller number of
transistors and as a consequence area
required will be small so lower area due
to smaller number of transistors then
lesser power dissipation there is no
static power dissipation and short
circuit power dissipation as we have
seen here although we are having path to
zero volt path to Hidde D but as you
know only one of the two paths will be
closed that means I there they will be
path to zero or they'll be path to VDD
there will be no path to the output
simultaneously to 0 for 0 infinity as a
result it will never form never need to
short-circuit power dissipation we know
that short circuit power dissipation
occurs because there is a path from VDD
to ground but here that kind of path
will never be established of course if
we follow design rule design rule 3 that
means if we follow design rule 3 only
then this will happen if we don't follow
it then this problem may arise but you
have to follow design rule 3 whenever
you are realizing circuits using pass
transistor line so these are the
advantages and obviously you will be
tempted to realize digital circuits or
realize boolean functions by using past
instil logic but before we venture to do
that let us have a look at the
disadvantages
first disadvantage is higher delay in
long chain of past and stirs this is the
first disadvantage you see whenever you
apply a number of transistors in series
say you'll be applying let's assume VDD
and you will be applied you see
realizing say there may be large number
of inputs so let's assume here we apply
BCD and so on so this is your input and
this is your output layout that means
whenever the signal is passing through a
large number of pass transistors what is
the outcome of this when the signal is
passing through a large number of pass
transistors it will lead to long delay
because each transistor is associated
with a resistance and a capacitance we
can model this as a somewhat like this
it a resistance and a capacitance and a
resistance and a capacitance and a
resistance and a capacitance capacitance
is connected to ground this is going to
get down if we have n transistors in
series we shall have n n R and C and
this is connected to your load
resistance so you are applying say input
here and the it is passing through in
number of resistors and capacitor to the
output this is your CL what is the
consequence of this this will lead to
large delay so
how do you estimate the delay whenever
the signal is passing through a large
number of transistors this can be
modeled as a single equivalent to as if
you have got one the distance and one
capacitance so these this network can be
modeled as this part can be modeled as a
single resistance and a single
capacitance where the resistance value
is equal to n into say R pass this is
the resistance of the pass transistor
and this is C is equal to I mean n into
C NC equivalent capacitance so
equivalent capacitance as if NC and
equivalent resistance is n R pass so
what is the time constant tau time
constant tau in this particular case is
equal to n into R pass into n into C
that means this is equal to n square R
pass into C so whenever we follow this
simple model we find that delay is
proportional to n square and obviously
for for input delay will be 16 times
that of the that of a single transistor
or when there are eight transistors in
cascade delay will be 60 is 64 times
obviously it will be very large however
it has been found that it is not so high
because this model that we have used is
a kind of pessimistic model and not
correct model a more accurate model can
be used more accurate model based on
what is known as el mode delay model
Elmore delay model
if we use this Elmo delay model this can
be modeled as as if this this and that
this time constant tau will be equal to
effective you can say is equal to this
is say r1 this is r2 r3 in this way let
us assume there are on n transistors and
similarly there's assume this is C 1
this is C 2 this is C 3 later on we
shall assume that they are all same so
then this delay then time constant will
be equal to R 1 into C 1 plus these 2
resistances are in series 2 which is
charging or discharging - capacitor so R
1 plus R 2 into C 2 plus in this way we
can say R 1 plus R 2 in this way RN into
CN we assume that all R and n all are
same then this this becomes equal to
this will become equal to n into n minus
1 by 2 into R into C this can be if all
C are same which is equal to C and all
are same R then the value will be like
this that means RC into n into n minus 1
by 2 so this will be the this will be
the time constant so the time delay
based on this model will be equal to 0.6
9 and into n plus 1 by 2 it will be n
into n plus 1 I believe plus 1 by 2 into
R into C so this will be the time
constant so even with this value let's
assume the value of n is equal to 4 so
when the value is equal to n is equal to
4 this is 4 into 5 by 2 that means it is
4 into 5 by 2 that means value is 10
that means it will be
ten into 0.6 nine so roughly 7rc so it
may not be 16 but 7rc that means when
the number of any value of n is equal to
four instead of 16 or C it is becoming
7rc so in this way we find that the
delay is increasing may not be at the
rate of I mean Square following square
law but it is definitely increasing at a
high rate so what we have to do to
overcome this problem to overcome this
problem the solution is we will insert
buffers you will insert buffers in
between the pass transistors let's
assume we use buffers at regular
intervals
maybe after few pass transistors the
buffer is inserted then again you have
got few such pass transistors here we
have assumed that buffer is inserted
after three 10 stirs so whenever we do
this and if the delay of these buffers
is not very large then this this this
and the overall delay can be reduced it
has been estimated following that elbahr
model this delay will be equal to zero
point six nine n by K where you have got
n pass transistors and delay then it is
introduced after K stages CL into our
pass into k plus k into k plus 1 by 2
plus n by K minus 1 I am NOT deriving
this but this is the delay of DD buffer
this is the expression that you will get
if you solve it you will get point 0.69
this will be equal to
Ciel our pass so this K this K will
cancel out into n into K plus 1 by 2 and
this part will remain same n minus K
minus 1 into T buffer oh how do you
minimize this to minimize this delay as
we know the simpler of doing it
differentiate it and equal make it equal
to 0 so you can what you can do to
minimize the value of this delay we can
have delta T PK by delta T that means
after how many stages K is the number of
stages after how many stages you will
insert a buffer we have shown
non-inverting buffer here so if we put
non-inverting buffer and to get the
value of PK we shall refer n shoot it
and then equate it to 0 and has been
found that K optimal value that you can
get will be equal to 1.7 again I am NOT
deriving it T buffer by our pass into CL
so this is the optimal value of delay I
mean the optimal number of stages that
will produce minimum delay and it has
been by sir by by by putting realistic
values of our path CL and delays or
buffer it has been found that the value
of K optimal is 3 or 4 that means if we
insert buffers at the interval of 3 or 4
pass transistors then the delay will be
minimized so this is how the impact of
long delay or pass transistors can be
minimized obviously you cannot nullify
it completely there is no way of doing
this but you can minimize it by using
this so whenever you are realizing
circuits by using pass transistor logic
you will see that after 4 or 5 stages a
buffer is inserted
and buffer will not reduce the delay
okay now what are the what is the second
disadvantage second disadvantage is
multi-threshold voltage drop
multi-threshold voltage drop that
problem we have already discussed here
as you see the transistor here we are
getting VDD minus VT n now this voltage
is is not really good in the sense that
if we use it to drive an inverter it
will not be it will lead to slow
operation of the dish in discharging
that means if this capacitor will be
discharged slower rate because instead
of five volt we are driving with four
volt so how this problem can be overcome
because normally we will say it will be
combining pass transistor logic with
static CMOS you may have to put
inverters static CMOS inverters along
with pass transistor logic so in such a
case you will encounter a relief s
problem so this multi-threshold voltage
drop particularly if we use say 210
purpose transistors in series and there
this one is used as an input to a next
stage then problem will be more severe
how we can overcome this problem this
problem can be overcome by using what is
known as swing restoration logic swing
restoration
so you have to provide a swing
restoration logic after you know
whenever you take the output to the next
stage what is the role of the swing
restoration logic it will raise the
voltage level to particularly the high
level to VDD so how it can be done
normally say suppose this is this is a
pass transistor logic and this is going
to an output so what will you do what
you can do you can put a weak PMO's
transistor and ground it so if you do
that as you know the voltage level will
be pulled to Hidde T through this weak
PMO's transistor and this is one
approach that can be followed another
approach is in addition in addition to
this weak PMO's transistor you can put
an inverter along with it weak PMO's
transistor that means this will be
applied to an inverter then you will
have be having a weak PMO's transistor
this is connected here and this output
will be coming from here so what will
happen in this even this inverter will
get high level voltage is VDD so this
week PMO's will pull the output to high
VDD level so this is this kind of swing
restoration logic either by using a
single weak PMO's transistor or along
with I mean weak PMO's transistor along
with an inverter can be used to restore
the voltage level here at this point we
can see we have raised the level so this
way this is this will serve as not only
swing restoration logic so showing
restoration logic along with inverting
buffer so this will act as an buffer so
this can be applied to the next strain
so you see this type of thing you have
to do for in realizing circuits
realistic circuits by using pass
transistor logic
so this is the second problem that we
shall face third problem is sneak path
sneak path I have already mentioned
about it sneak path occurs when because
of the problem of logic design there is
path to VDD and ground as you can see
here say here you are supposed to get F
but what has happened simultaneously for
some input combination in this
particular case a is equal to 1 B is
equal to 1 C is equal to 1 D is equal to
1 you can see there is a path from 1 to
0 so you can see here the voltage will
be neither high nor low something in
between and not only that there'll be
that kind of it will lead to
short-circuit power dissipation so this
so you have to design such that there
should not be any slick path which I
have already mentioned as the third rule
so you have to design in such a way so
that there is no sneak part how can it
be avoided
so how can we avoid
sneak path sneak path can be avoided by
using multiplex
multiplexer based circuit design so use
multiplexer this system design what is a
multiplexer multiplexers as you know it
has got multiple input and a single
output you can multiplex the inputs so
suppose you have geared you have it
you're familiar with said to input
multiplexer so here there are two inputs
and there is a control inputs and you
produce the output so this is the
control signal and these are the two
inputs that we apply this is known as 2
to 1 MUX so in a similar way you can
have 4 to 1 MUX say 4 to 1 multiplexer
in this case you will be having 4 inputs
and there will be a single output and of
course you will require 2 signals to
control which input will be selected to
be connected to the output so
essentially the role of this control
signal is to control the path to one of
the two inputs in this case and here to
one of the paths one of the four paths
in this particular case how can you
realize this multiplexer you can realize
multiplexer by using switch logic using
pass transistors for example this this
particular 2 to 1 multiplexer can be
realized in this way so this is a 2 to 1
MUX here is 1 inputs the first input
here is second input what you do here
you apply a here and in this case apply
the control signal a bar so control
signal a bar is here and control signal
is here that means you
control signal is a this is one this is
two
and here you are getting output V out so
that means when a is equal to one the
the one input is connected to the output
when a is equal to zero is equal to zero
then this input two is connected to the
output this is how you can realize a a
boolean function I mean you can
multiplexer is realized in a similar way
a 4 to 1 multiplexer can be realized in
this manner here you will require two
pass transistors in each path of course
and there will be four paths there will
be four paths so all the four paths are
tied together and here it would you say
see out and 1 2 1 2 3 4 and let us
assume these are a and B so what you
will do this will be a B and this is a B
bar a bar b and a bar b bar so what will
happen when both the inputs are 0 then I
mean what both the inputs are 1 path 1
will be connected when a is 1 B is 0
then this path will be connected path
will be connected for an a behavior a is
0 B is 1 then path 3 will be connected
to the output when both are 0 then path
4 will be connected to the output
question is how this multiplexer can be
used to realize boolean functions it can
be very easily done from the truth table
for example say a function f can be let
us assume it is a function of two
variables can be always expressed as in
terms of say G 1 G 1 and F say 0 0 sorry
Z 0 F 0 0 plus G
1 EPSA 1 plus G 3 f 1 0 and plus G 4 F 1
1 that means suppose a and B these are
the two inputs and 0 0 0 1 1 0 1 1 then
depending on whatever is the say this is
f say let's assume we are realizing 1 0
1 0 then Z 0 Z 1 Z 3 Z 4 can be directly
taken from the truth table that means F
0 if the Z 0 of hello of Z 0 is equal to
1
hello op g 1 is equal to is equal to 0
value of G 2 is equal to 1 value of G 4
is G 3 is equal to 0 that means what
will you do if this is the multiplexer
you will apply a and B as control input
and you will apply Z 0 G 1 G 2 and G 3
which are essentially boolean function I
mean boolean variables you can see
depending on the function you are
realizing they will be having 0 or 1 so
accordingly we apply and this will
realise it so it can be proved that a
multiplexer for import multiplexer
multiplexer can realize any function of
two variables not only I mean later on I
shall prove also instead of applying 0 &
1 here if you can apply one variable
here else instead of say suppose there
is another variable C what you can do
you can apply 0 1 or C and see - if you
are allowed to do that that means say
for input MUX can realize any function
of three variables you can expand around
a and B then these functions G 0 G 1 G 2
G 3 these are known as reduced functions
reduced functions
these reduce functions you can find out
those reduced functions will be either
constant that means zero or one or
function of the third variable C that
means either C or C does so those you
can apply 0 1 C and C - and you know you
can realize any function that means
using pass transistor logic you can
realize boolean function using
multiplexer as the kind of building
block where multiplexer is realized
using pass transistors so this is how it
can be done and it can be proved that
this is free from all the problems that
I discussed that means all the design
rules which I have mentioned is followed
here
none of the three designs rules that I
have told is violated in this case so
you can realize functions in this way
and that is the reason why multiplexers
are known as they are known as you know
it they can since they can realize any
function they're considered considered
as universal logic gate
so since they can realize any function
so in fact later on if you study FPGA
field programmable gate array
there are multiplexer based field
program will get gate array by active
their multiplexer is used as building
block of digital circuits
so how multiplexer is realized that is
no concern there but any boolean
function can be expressed in terms of
multiplexers and this is how it can be
done so we find that this is a technique
by which you can realize boolean
functions and using multiplexer as
building block okay let me consider
another very important disadvantage
complimentary control signals we have
already seen that in some cases you have
to apply control signals in the
complemented form if we consider the
network and no multiplexer within the
multiplexer network we can see B by B
bar a bar these are also present that
means you have to apply both the
variable control variable and its
complement to control the
pass-transistor logic network that means
this is a disadvantage
you have to it must you have to generate
the control signal in other words you
have to use what is known as dual rail
logic dwell the logic so you will
generate F as well as F bar so that F
and F bar can be used as control signal
to the next stage so these are the main
drawbacks and advantages that we have
discussed sorry now we can summarize
what we have discussed in today's
lecture I have discussed about
introduced the basic concept of persons
the logic discussed about the logic
design rules discussed about their
advantages and disadvantages and discuss
techniques how to overcome these
problems in my next lecture I shall
discuss about how you can realize
complicated boolean functions using pass
transistor logic that means systematic
technique for logic design and also
there are some logic families pass
transistor logic families which are
which have been proposed in the last
couple of years so I shall only
introduce the pass transistor logic
family to you thank you