Switching Power Dissipation - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)

you
hello and welcome to today's lecture on
switching power dissipation we have
discussed various types of MOS circuits
in a bottom-up approach using a
bottom-up approach we started our
discussion on MOS transistors various
characteristics of MOS transistors then
we discussed about the realization of
different types of MOS inverters using
MOS transistors after that you have
discussed different types of
combinational circuits that you can
realize using MOS transistors we have
discussed guest gate based logic
circuits like static CMOS dynamic CMOS
and also switch based logic circuits
like pass transistor logic then we have
covered the most memory devices and
finding at the in the last lecture we
have discussed about finite state
machine so that gives you a complete
background of different types of MOS
circuits that you will encounter in your
VLSI circuits and systems in other words
now this stage is ready to discuss about
low-power aspects and today we shall
start with our discussion on sources of
power dissipation first lecture will be
on switching power dissipation that
means that is one of the most important
component of the sources of power
dissipation so here is the agenda of
today's lecture first I shall give a
brief introduction about types of power
dissipation then discuss about the
classification of sources of power
dissipation dynamic power and there are
three components as you know switching
power source circuit power and blessing
power and also there is another type of
power dissipation that is called static
power dissipation that we shall discuss
later but based on this dynamic power
what are the degrees of freedom that I
shall discuss we
at the end of our discussion on
different types of sources in this
lecture we shall focus on switching
power dissipation but before I do that
let us discuss about what do you really
mean by power and what are the different
types of power dissipation that we
encounter in digital circuits one of the
most important sources of power
dissipation another important power
dissipation is peak power so what is
peak power peak power if you plot the
power dissipation of a circuit over a
period of time this is the power which
is a function of time you will find that
it is not constant so sometimes it is
more sometimes it is less and so on so
it will be somewhat like this so it is a
function of time you will be asking why
this kind of peak I mean maximum power
occurs it occurs in many situations for
example when you are turning the power
of a laptop or a computer then at that
point it will consume large power you
will be asking how the peak power which
is essentially the instantaneous maximum
power but they say that that is drawn
from the power source how it affects the
behavior of the circuit actually
whenever a there is a surge in power
dissipation that means suddenly it
increases lot of current flows to the
power lines that means power is drawn
from the supply line and also that
current passes to the ground so the
supply and ground lines through those
lines heavy current will flow suddenly
and because of that it will it will lead
to some kind of transients or on
different parts of the circuit that
means it will affect other components of
the circuits that means it will lead to
glitches it will lead to Drew
and so on that means as a consequence of
this peak power sudden surge of power
power drawn by the circuit some bits of
a computation may be erroneous that
means some or whenever you are writing
or reading from memory you may be
reading wrong data when there well well
that transient occurs so in other words
peak power affects the effects the
circuit in terms of correct output that
means he may not get correct output in
other words reliability of the circuit
is affected so so this is this this is
the peak power then second one is the
average power what is the meaning of the
average power for example for this
particular waveform the average power
will be somewhat like this so maybe it
will be like this this is the average
power so this is average over a period
of time period set T so if you have a
Ridgid over a feed time period t then
this is the current this is the power
dissipation in what way this average
power is important in fact the average
power is very important from the
viewpoint of packaging and cooling cost
that means the power dissipation over a
period of time that has to be dissipated
using the cooling and packaging
arrangement so the packaging and cooling
cost is affected by the average power
not only that the average power affects
the cost of the battery because you are
drawing the power source from the
battery or it may also affect the power
circuits but for example regulated power
supply transformers which are used to
generate the DC power so those will be
affected rather the weight of the system
volume of the system and the packaging
and cooling cost these will be affected
by the
average power dissipation so average
power is very important from wherever
you are your circuit is operating from
battery because the size of the battery
will be large and it will not last for a
long duration if the average power is
high however whenever you reduce the
average power the peak power is also
reduced that is the reason why most of
the time we shall be focusing on average
power reducing the average power and
simultaneously the peak power will be
reduced now here for example the power
in watts is plotted and p1 is the peak
power for for a duration of time set T 1
0 to t1 and similarly average power
dissipation p2 is for another duration
maybe t2 that means that this peak power
dissipation at this moment and that this
moment may be different average power
dissipation and during the time t1 or
during type t2 may be different now
there is another very important concept
that is energy power and energy these
two are although they are different
sometimes we use them interchangeable in
what way they are related let us try to
understand what do you really mean by
energy energy is the actual I mean
energy I mean energy what is drawn over
a period of time from the power source
that means it is power into time that is
your energy for example in this
particular plot we have that power
dissipation was P 1 and over a period of
period of time T 1 so e 1 is the energy
which is represented by the area under
this rectangle area of this rectangle so
that means this energy
say if this is the power dissipation p1
average power dissipation p1 over a
period of time t1 and say another power
dissipation which I have shown that is a
average power dissipation p2 over a time
period t2 then energy here obviously
time and here P so energy e1 is the area
of this rectangle similarly the area of
this rectangle is this year again e to
is area covered by this rectangle that
means energy e1 is equal to p1 average
power dissipation into t1 similarly e 2
is equal to P 2 P 2 into t2 now you may
be asking in what way energy affects
your circuit particularly for battery
operated systems energy is very
important because whenever battery is
fully charged some amount of energy is
transferred from the charging source and
that energy has to be used by the
battery for for the for performing
computation and other thing so you have
to essentially minimize energy whenever
you think about battery operated systems
that means whenever we say low power
essentially we are meaning low energy
but sometimes we use these two
interchangeably although they are
different so we have discussed about
different types of power dissipation and
relationship between power and energy
now let us focus on the sources of power
dissipation in CMOS circuit the sources
of the different sources can be divided
into two basic categories dynamic power
and Static power so what do you really
mean by dynamic
power dynamic power dissipation occurs
when the circuit is in operation when
the circuit is in action you have
applied a supply voltage you have
applied clock you are changing the
inputs outputs are changing that we call
the circuit is in operation or in action
and that time whatever is the power
dissipation we call it dynamic power on
the other hand static power dissipation
is when maybe the inputs I mean the
power power source is there but inputs
are not changing clock is withdrawn then
we call it static power and a static
power dissipation as we as we have seen
in case of civil circuits it is
essentially leakage power dissipation so
and again the dynamic power has got
three components which I mentioned in my
first lecture the ninety the three
components are switching power
short-circuit power and glitching power
so these three different types of power
dissipations occur when the circuit is
in operation and which are categorized
as dynamic power and switching power is
the most important component which I
shall discuss in this lecture what we
really mean by switching power and why 2
occurs switching power occurs due to
charging and discharging of load and
parasitic capacitors as you have seen in
a CMOS circuit there are a lot of
capacitances gate capacitance then
capacitance interconnect capacitance and
so on various types of capacitances are
present in a circuit and those
capacitances gets charged and discharged
during normal circuit operation and that
leads to power dissipation and that is
known as the switching power dissipation
and let us look at a simmer circuit M we
have seen the basic have I mean the
generic schematic diagram of a CMOS
circuit is like this you have a pull-up
Network
made off in most P Mo's transistors and
you have a pulldown network made of n
MOS transistors and we have a load
capacitance CL that is how we model it
although CL is a is shown as a lump
capacitance it is essentially comprises
many capacitances including gate
capacitances interconnect capacitances
and various other types of capacitances
now in this situation how the the the
switching power dissipation occurs now
let us see how it is occurring whenever
the output is changing from say 0 to 1
let us consider a very simple circuit
say an inverter you have an inverter for
the sake of simplicity and this is
connected to VDD and this is connected
to input now you have a load capacitance
CL
connected here suppose initially the
input wires a1 and it had changed from 1
to 0 input V it what will happen to V
out V out will change from 0 to 1 then
what will happen that means initially
the charge across this capacitor charge
that was stored in this capacitor was
zero now it will charge through this
transistor because when the input
voltage is zero that time this is off
and this is on and as a consequence this
capacitor will charge through this P MOS
transistor through is P Mo's transistor
it will charge and this while while it
charges some power will be dissipated in
this P boost and step because it is a
resistive component and out of the total
energy that is drawn from this power
source may be battery or some power
supply
some will be lost as the form of heat
because when current passes through a
resistive load the that that gets that n
power dissipation gets dissipated in the
form of heat on the other hand part of
the energy will be stored in this
capacitor CL later on we shall see what
is the energy that is drawn from the
battery for charging a capacitor and how
much energy is stored in this capacitor
now suppose it changes flow it changes
now from the same circuit now the output
change input changes from V in now
changes from 0 to 1 then what will
happen then what will happen this will
become op and this will become cold and
as a consequence as I told some energy
was stored in this capacitor that energy
that charged energy means that will be
stored in the form of charge that will
get dissipated through this n MOS
transistor that means the the energy
that was stored in this capacitor while
after charging from VDD that will now
get dissipated through this n MOS
transistor and that that it will be now
the charge will become zero that means
whatever energy that was drawn from the
power source part of the energy is
dissipated while charging and part of
the remaining part of the energy gets
dissipated while discharging that means
when the output goes from one to zero as
it is shown in this diagram so this is
this is the charging current so for a
general CMOS circuits the pull-up
network is responsible for power
dissipation while charging and pulldown
network which may be a complex network
that is responsible for power
dissipation while discharging so from
the capacitor it gets discharged to the
full level Network now we can calculate
the calculate the power dissipation let
us let us now proceed
to calculate the various power
dissipation that occurs in a circuit in
this part in this type of circuit so how
much energy is drawn so during
transition from 0 to 1 how much energy
is drawn from the power source let us
find out that so energy drawn e02 1 is
equal to 0 to VDD this capacitor is
charging from 0 to VDD and power
dissipation and time the time over a
period of time this is happening and as
you know current will pass through this
part of the circuit and that will lead
to power dissipation and what is the
expression for current this current is
not fixed that current will be equal to
I T and this will vary with time CL into
DV 0 DT what it DV 0 DV 0 v 0 is the
output voltage so rate of change of
output voltage with time into the into
capacitance values the load capacitance
is the instantaneous current that will
be passing through this part of the
circuit so if we substitute it here then
we shall get CL will come out this will
become 0 to VDD into that DV 0 VD D so
we shall use zero DT 0 to 1 VDD and it
will be C L energy is the 0 to VDD and
CL DV 0 and this will be equal to power
is voltage into current power is voltage
into current that we have missed here so
whether will be V DD factor VT is equal
to VT is equal to I T into VDD this is
the power dissipation so VDD we factor
with here so this if we evaluate this
will become CL VDD square so clvdd
square is the energy that will be drawn
from this power source so we find that
that an energy of clvdd square will be
drawn from the power source now you will
be asking for different types of the
charge charging current will this
expression be same or in other words
what I am telling suppose you charge is
using a constant current source from a
constant current source will it be same
whenever we do it through a register as
you have done in this case actually the
as the capacitor is charged from 0 volt
to VDD this energy will be same
irrespective of the way you charge it
that means the nature of charging
current can vary like this as it happens
in whenever you charge it through a
register or it may be a linear current
will fall over a period of time when it
charges to VDD so irrespective of that
this will be the energy that will be
drawn from the power source so that is
the reason why there is no other
parameter or factor now out of this
energy how much is actually stored in
the capacitor and how much is gets
dissipated in that load resistance load
resistance in this particular case is P
most and
the network so let us calculate that
that means the energy that is being
stored in this capacitor EC will be
equal to then let us say let us consider
the time taken is 0-2 T is v-0 I T into
DT v-0 is the output voltage which is
also a function of v-0 and current that
is I T and DT so this we can write as 0
to VD D if we substitute I T here it
will become CL V 0 DV 0 because this DT
DT will cancel I T as you have seen is
equal to CL DV 0 DT so this DT and this
treaty will cancel out we shall get DV 0
so if we evaluate this we shall get half
CL V DD square so we find that energy
that is being stored in the capacitor is
half clvdd square square that means out
of clvdd square that the energy that was
drawn from the power source
half body half of it is getting stored
in the capacitor that is being stored in
the capacitor load capacitance and
remaining hop-hop clvdd square gets
dissipated in the P Mo's transistor
Network
or it can be a single biggest transistor
in the case of an inverter okay and this
remaining half of energy will be
dissipated whenever you know the output
switches from 1 to 0 so we find that
half of the energy that is drawn from
the power source gets dissipated while
charging the capacitor to raise the
voltage from 0 to 1 and remaining half
is getting dissipated when it is when
the output is switching from 1 to 0 okay
now there may be some
there may be some some situations where
if we apply a square wave to the input
of a circuit for example we have an
inverter is an inverter and here we have
applied a clock instead of an e input
obviously in each cycle the output will
charge it it will sever the input is 0
output will be 1 and when it is output
is a 1 it will be 0 that means in each
cycle charging and discharging will take
place so that means wherever you have
applied a clock or in other words when
the output changes in each cycle of a
clock then what will be the power
dissipation so power dissipation PD
we'll be equal to 1 by T because 1 by T
is the time of this period energy was
clvdd square so over a period of time T
so whenever you calculate power
dissipation it will be 1 by T into clvdd
square or that is equal to CL VDD square
into F in other words the power
dissipation will be equal to the clock
frequency proportional to the clock
frequency so clvdd square F that is the
power dissipation that will take place
now you see in addition to power
dissipation in the load we consider a
circuit like this let us consider a
simple nor gate so in this in addition
to these inputs a and B we have got so
we have got another load this is CL and
here say node A or you can say
intermediate node say C I the
capacitance here is CI C 1 and node 1
let us assume now whenever this
particular node is charging and
discharging it may so it will what will
happen this capacitor also will charge
and discharge however if this in this
particular case it is the switching will
not be from 0 to VDD because as you know
whenever the charging takes place
through a n MOS transistor it can charge
up to VDD minus V T so as a consequence
the power dissipation that means energy
that will be drawn will be equal to VDD
into c1 into
deedy into VDD minus VT because it will
charge it will not charge up to VDD but
it will charge up to will divide you
minus 50 that means in this expression
what we got here this DV 0 will not
charge from 0 to VDD but it will charge
from 0 to VDD minus VT so as you can see
Keynes you will get here CL VDD into VDD
minus VT so you will be getting the
power dissipation in an internal load
that will not be clvdd square but CL VDD
into VDD minus VT now okay
so this is what will happen now let us
consider another very important concept
that is the switching activity
probability that the output will be 0
and and how did they turn p1 I mean when
the output will be 0 and when the output
will be 1 why this is necessary let us
try to understand you see whenever we
are considering a circuit say NAND gate
will the output change in each and every
clock cycle it will not change the
output will change depending on the
functionality of the circuit so we can
calculate the probability of transition
to 0 and 1 and find out the the find out
a parameter known as switching activity
in this particular whenever we derive
this expression we assume that there is
transition at each and every cycle but
that will not happen because you are not
really applying a clock to a circuit it
is a complex function depending of the
nature of the imports output will change
and so this will not change in each and
every clock cycle so to take into
account we have to take another factor
which is known as switching activity
switching activity what is switching
activity switching activity is
represented by alpha how can you
calculate switching activity switching
activity is defined as probability of
transition from 0 to 1 and this is equal
to p 0 into p 1 what is p 0 and P 1 p 0
is actually the probability that a
circuit will remain we will attain a
value 0 and what is we're sorry p 0 is
the probability that a circuit will at
any value 0 and p 1 is a probability
that a circuit will attain a value 1 say
let us consider the NAND gate that I
have drawn we know the truth table say a
B a B and say F for 0 0 0 1 1 0 1 1 so
output will be 0 only for 1 1 and for
all the other three conditions the
output will be 1 when any one of the
input is 0 output will be 1 now what is
the probability of this output to have
the value 0 we can find out that there
are four possible possibilities so out
of four possibilities only once it can
happen so in this particular case the p0
will be equal to 1 by 4 and what is the
value of P 1 out of 4 combinations 4
possibilities input possibilities the
output can have the value 1 3 times out
of 4 so 4 ability is 3 by 4 that means
if we take this over a long period of
time the switching activity or
probability of transition from 0 to 1 1
1 to 0 will be equal to this 1 by 4 and
1 by 3
this will be equal to 3 by 16 that means
the switching activity will be 3 by 16
and this is the case for for a case for
a red gate we can generalize it we can
generalize it suppose p0 is the
probability that the output will have
the value 0 will be is equal to say n 0
by 2 to the power n n0 is the number of
zeros in that truth table you see we
write a truth table number of zeros in
that truth truth by the total number so
that will be equal to n0 is total number
zeros by these are the total number of
combinations so if if p0 is equal to n 0
by 2 to the power N and P 1 will be
equal to n n 1 by 2 to the power n and
obviously n 1 will be equal to 2 to the
power n minus n 0 because they are
related when the output is 0 it cannot
be when the output is not 0 it will be 1
so therefore p 0 to 1 for a general
boolean function can be written as n 0
by 2 to the power n into 2 to the power
n minus n 0 by 2 to the power n so that
is equal to n 0 into 2 to the power n
minus n 0 by 2 to the power 2 n so you
find this is the probability of
transition from 0 to 1 and 1 to 0 so we
can say this is the switching activity
now for different types of gates the
value will be different for inverter it
is 1 by 4 how does it 1 by 4 because in
an inverter as we know you have got only
one input so probability that the output
will be 0 is half and probability that
the output will be 1 is also half that
means p 0 to 1 for inverter is equal to
1 by 4 and 4 then and and gates you
already discussed it is equal to 3 by 16
similarly for NAND and nor gates it will
be 3 by 16
however for 2 input XOR gate it will be
1 by 4 why so because in case of XOR
exclusive or gate say a and B are the
two inputs and it is the function of X
or so 0 0 0 1 1 0 1 1 exclusive odd that
means when it will be when the output
will be 1 it will be 0 here and it will
be 0 here it will be 1 here it will be
here so output is has got two zeros and
two ones that is the reason why you are
getting p0 is equal to 2 by 4 and P 1 is
equal to 2 by 4 therefore p 0 2 1 will
be equal to 1 by 4 hopping to 1/2 so we
find 4 exclusive or gate it will be 1/2
now let us consider how the switching
activity changes with the increase in
the number of inputs as the number of
inputs is increasing how it will change
we can see for an XOR gate as you
increase the input it remains equal to 1
by 4 that is 0.25 why so because we have
seen in the truth table always it with
the number of zeros and number of ones
will be same then that will be half of
the total number so this value will be
always equal to 1 by 4 X or as we
increase the Fanny number of inputs on
the other hand for NAND and down and or
gates it will change over time you can
see the expression that we got is this
sense 0 into 2 to the power n minus n 0
by 2 to the power 2 to the power n 2 N
and this expression as n increases it
will reduce because this factor is bored
I mean this will increase
this will have larger value compared to
this so we find that for 400 is equal to
2 this is little more than a little less
than 0.2 that is 3 by 16 and then it
will become close to 0.14 3-input and in
this way it will reduce what message
does it give is there any message that
we are getting from this
that means the switching power
dissipation of a gate will be less if
the thread is reading is more that means
the power dissipation of the gate or the
load capacitance charging and
discharging will be less if the fennan
is more later on we shall see what
impact it has got in the realization of
a circuit particularly whenever you go
for loop or realization of no.4 circuits
now so so far we have seen how it
happens in case of simple gates and gate
or gate NAND gate nor gate and so on but
unfortunately in our real life the gates
will not be as simple as this it will be
more complex so however the wherever it
is a complex gate then we cannot really
calculate the way we have formed so for
a complex gate the switching activity
depends on two factors the topology of
the gate and the statistical timing
behavior of the circuit so these two
will affect the the switching activity
of the circuit so let us now define
switching activity for a complex gate
and find out an expression for it let n
be the number of inputs
number of 0 to VDD output transitions
these are the number of output
transitions that will occur in a circuit
and in the time interval in the time
interval 0 to n that means out of n
possible transitions and then is the
number of transitions that is occurring
from 0 to VDD so total energy drawn en
en will be equal to we know for each
transition the from 0 to 1 the energy
rod is CL VDD square and so the total
total energy that will be drawn will be
equal to clvdd square into n n now what
is the or dissipation average power
dissipation that will be equal to limit
n tends to infinity for large value of n
we shall take an average en by F into en
by n into F F is the clock frequency so
this we can this value up here we can
substitute here and that will lead to
limit n tends to infinity n n by n into
CL VDD square into F this particular
factor is given the simplified term that
is alpha that means this limit n tends
to infinity n n by n this value is given
the variable value given the symbol
alpha that is switching activity
switching activity therefore you can say
that average power dissipation is equal
to alpha CL VDD square and F and that is
the average power dissipation on the
load capacitance CL obviously this is
not the only power dissipation that will
occur there will be power power
dissipation in the internal loads we
find that there are various internal
nodes and here a three input NAND gate
is given so here you can see in this
three input NAND gate the there are two
additional nodes at this point between
the junction of q4 and q5 and between
the junction of q5 and q6 so these
capacitors also will get charged and
discharged so for a generalized CMOS
circuit what is the switching power
dissipation P switching will be equal to
alpha L CL alpha L is the probability of
time the switching activity of the load
capacitance at four alpha l CL VDD
square F then it means it may have a
number of internal nodes which is
represented by I I to say maybe n nodes
are there I is equal to 1 to N and you
have to take summation of this power
dissipation that will be equal to alpha
into CI CI is the load capacitance alpha
I is the probability switching activity
at that node into VDD into VDD minus VT
because in this case as we have seen we
have already seen that in such
situations whenever the you are charging
and discharging this capacitor or this
capacitor C 1 and C 2 it will not charge
to VDD but it will charge to VDD minus
VT that is the reason why you have used
the expression Brady divider
vt here so this is the switching power
dissipation in a general symbol circuit
okay now so far we have assumed that
inputs are equal what do you mean by
equal say a particular gate has got two
inputs a and B that probability of
occurence we assumed is same but it will
not be true in real life some inputs
will come from one source another input
will come from another source so our
serving push will be generated by a
complex circuit as a consequence the
imports will not be equal probable their
probability of occurrence will not be
same earlier we assume they are same or
we assume probability of occurrence is
one so in such a case how do you
calculate the the switching activity the
probability of transitions at the output
depends on the probability of the
transitions at the primary inputs so we
have to take into account the
probability of transitions at the
primary input how do you take it into
account let us consider a two input NAND
gate in case of a two input NAND gate we
know that p0 is equal to P into P B you
know p p0 means with the P what is p0
for a two input NAND gate you have a two
input NAND gate a and B so PA is the
probability that this node will become
one probability of transition to one
that P P is the probability of
transition to one for this node B and
you can see when the output can become 0
when both the both the inputs are 1
therefore p 0 will be equal to PA into
PB and however your P 1 will be equal to
1 minus PA into PV
so you find that that p0 is not is no
longer
1x4 or p1 is no longer 3 wherefore in
this particular case because it all
depends on the probability of transition
to 1 and probability of transition to 0
that will be different therefore p 0 to
1 which is the switching activity which
will be equal to p 0 into p 1 for an and
gate will be equal to 1 minus P a P B
into into P a P B so you find that
whenever the inputs are not equal in
this way we can find out the switching
activity and similarly the switching
activity of the or gate we can find out
that for a nor gate it will be equal to
1 minus P a into 1 minus P B probability
of transitions to 0 and probability of
transitions to 1 and you can multiply it
the or gate this is the situation for
XOR gate it will be equal to 1 minus PA
plus PB minus 2 P a P V into PA plus PB
minus 2 P a P so we find it is a little
complex whenever we take into account
the probability of transitions for
different inputs coming from different
sources now in fact we with the help of
with the help of a simple NAND gate if
the output is coming from a NAND gate we
can find out the probability of
transitions for example say we have got
a NAND gate and as we know the inputs
may be equal here but here the
probability of transition to 0 and 1 are
not agree probable so as we know slop or
suppose this is when the circuit is in
the zero and this is when it is 1 what
is the probability of transition from
zero to
zero for a NAND gate for a NAND gate we
know that 0 0 0 1 1 0 1 1 output is 0
only here so in this case these are 1 so
probability from 0 to 0 is 3 by 4 into 3
by 4 probability from for a transition
from 0 to 0 will be 3 by 2 4 into 3 by 4
probability of transition from 0 to 1
will be equal to from 0 to 1 it will be
equal to 1 by 4 into 3 by 4 similarly
probability for transition from 1 to 1
will be equal to 3 by 4 into 3 by 4 and
probability for transitions from 1 to 0
1 to 0 will be equal to 3 by 4 into 1 by
4 so we find that that probability of
transitions to 0 1 and the output of an
and gate is not same 1 to 0 and 0 to 1
that is the reason why this this this
this type of probabilities are to be
taken into consideration
and in a complex circuits that
computation of switching activity is not
very simple however it can be done the
way the way I have the explains now
there is another complexity in our
circuits earlier we assume that all the
imports are independent so if the inputs
are coming from different sources and
there is no correlation among them
obviously they will be independent but
in reality that cannot be so so there
can be some some inputs I mean some
input will appear and again the function
generated by it will converge with
another signal for example let us
consider a simple circuit here I have
taken a 2 level circuit here it is an or
gate two input nor gate with input X 4
x2 and here we have another gate with
input X 3 and X 4 so we find that the
probability these X 1 X 2 X 3 and X 4
all are independent so the switching
activity at this point will be 3 by 16
similarly the power switching activity
will be 3 by 16 and if we consider the
output the switching activity here will
be 63 by 256 but suppose these two are
tied together these two are tied
together then what will happen then what
will happen the switching activities
this output and this output are no
longer independent here this isn't
independent these two are independent
inputs but here these two are not
independent when as a consequence here
the probability of transitions will be 3
by 5 into 5 by 8 and as a consequence
the the the switching activity becomes
more 15 by 64 and in fact it can be
illustrated with a more simple circuit
for example we have a simple NAND gate
now in this case we have applied two
inputs a and B and as we know the
switching activity here will be 3 by 1
16 now suppose what we do we apply an
inverter and apply to the 2 inputs in
this case what will happen what will be
the switching activity so in this case
whenever this is 0 this is 1 and
whenever this is 1 this is 0 so what
will be that switching activity here and
surprisingly you will find that since a
and B these two are correlated the
switching activity will be 0 here
because output will be always 0 as you
know if in an and gate whenever you
apply any input 0 sorry
yeah input 1 output will be always 0 the
switching activity will be 0 output will
be always remain 1
so whenever you apply this kind of thing
that means in in this type of wherever
there is some convergent inputs the
convergent outputs are taken together
then the switching activity increases
and in this particular case we have seen
it has decreased that means it has
become zero switching activity is
becoming zero so this type of this
mutually dependent inputs you have to
take into account when multi-level
network of complex gates are considered
the inputs of a gate at a particular
stage might not be independent so you
have to take into account this in your
circuit okay with this let us come to
the end of today's lecture we have
discussed about the one very important
sources of power dissipation that is
your switching power dissipation in CMOS
circuits and we have seen it is
proportional to what parameters you have
to consider the important parameters on
which it is depends CL node capacitance
or if it is internet load CI then it
will dependent on VDD and particularly
we find that there is a square law
dependence on VDD square and also it
depends on frequency so from this what
is our observation or observation why we
are studying sources of power
dissipation essentially we are trying to
identify the enemies so here our enemies
are capacitance supply voltage and
frequency so we find we can when if we
want to reduce switching power we have
to reduce load capacitance we have to
reduce supply voltage and we have to
reduce frequency so later on whenever we
shall discuss techniques for reducing
switching power dissipation we have to
focus primarily on supply voltage
because the switching power dissipation
heavily depends on supply voltage
and of course the another parameter I
did not mention that is your switching
activity so these are the parameters on
which we shall concentrate and we have
to minimize or reduce one of these four
parameters to reduce switching power
dissipation so with this let us come to
the end of today's lecture thank you
you
you