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Dynamic Power Dissipation - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)
FAQs on Dynamic Power Dissipation - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)
| 1. What is dynamic power dissipation in VLSI circuits? |  |
Ans. Dynamic power dissipation refers to the power consumed by VLSI circuits during the switching activity of transistors. It occurs when transistors switch states from 0 to 1 or from 1 to 0, causing a capacitive load to be charged or discharged. This power dissipation is directly proportional to the frequency of switching and the load capacitance.
| 2. How is dynamic power dissipation calculated in VLSI circuits? | |
Ans. The dynamic power dissipation in VLSI circuits can be calculated using the following formula:
Pdynamic = 0.5 * C * V^2 * f
where Pdynamic is the dynamic power dissipation, C is the load capacitance, V is the supply voltage, and f is the switching frequency. This formula considers the energy consumed during each transition and the total number of transitions per second.
| 3. What are the factors that affect dynamic power dissipation in VLSI circuits? | |
Ans. Several factors can affect the dynamic power dissipation in VLSI circuits, including:
- Switching activity: Higher switching activity leads to more dynamic power dissipation.
- Load capacitance: Higher load capacitance increases the power dissipation.
- Supply voltage: Higher supply voltage results in higher power dissipation.
- Switching frequency: Higher switching frequency leads to increased power dissipation.
| 4. How can dynamic power dissipation be reduced in VLSI circuits? | |
Ans. There are several techniques to reduce dynamic power dissipation in VLSI circuits, including:
- Clock gating: Turning off the clock signal to inactive circuit blocks reduces power dissipation.
- Voltage scaling: Lowering the supply voltage reduces power dissipation, but it may affect circuit performance.
- Power gating: Completely shutting down inactive circuit blocks reduces power dissipation.
- Data encoding: Using data encoding techniques reduces switching activity and power dissipation.
- Low-power design methodologies: Implementing low-power design techniques, such as using power-efficient logic styles and optimizing circuit architecture, can significantly reduce power dissipation.
| 5. What are the implications of high dynamic power dissipation in VLSI circuits? | |
Ans. High dynamic power dissipation in VLSI circuits can lead to several implications, including:
- Increased energy consumption: High power dissipation results in increased energy consumption, leading to higher operational costs.
- Heat generation: Higher power dissipation leads to increased heat generation, which can affect circuit reliability and performance.
- Limited battery life: In portable devices, high power dissipation reduces the battery life, requiring frequent recharging.
- Thermal issues: Excessive heat generation due to high power dissipation can cause thermal issues, leading to device failure or degradation.
Text Transcript from Video
hello and welcome to today's lecture on
dynamic power dissipation we have
started our discussion on various
sources of power dissipation in CMOS
circuits in the last lecture and I have
mentioned about two different types of
power dissipations whether you can
categorize the social support
dissipation into two types dynamic and
Static and in the last lecture I have
introduced the switching power
dissipation which is one of the
components of dynamic power dissipation
and today we shall continue our
discussion on switching power
dissipation and then as you shall see
later on I shall discuss about the short
circuit power dissipation which is
another component of dynamic power
dissipation so here is the agenda of
today's lecture essentially I shall
briefly recapitulate about the types of
power dissipation then classification of
sources of power dissipation as I
mentioned we are focusing on dynamic
power in this lecture I have already
started discussion on switching power
dissipation and it will be followed by
short circuit power dissipation and
glitching power dissipation and later on
I shall discuss about the degrees of
freedom that means what are the
parameters you can use to reduce dynamic
power dissipation rather what is your
handle in reducing the power dissipation
we have discussed about three types of
power in my last lecture peak power
average power and this definition
difference between power and energy as
you know peak power is very important
because at any instant of time what is
the maximum power that is being that is
taken that is drawn by the
circuit in operation is very important
for reliable operation of the circuit
and as you know because of the peak
power there is transience on the
powerlines and that may lead to glitch
and error in the signal we are not going
to discuss in detail today similarly the
average power is important particularly
for battery operated embedded systems
battery operated portable systems where
the life of the system depends on the
battery battery and how long the battery
can sustain the power and on the average
how much power dissipation is taking
place that is very important that's why
most of our discussion will be based on
this average power dissipation and I
have mentioned about the difference
between power and energy as we shall see
actually in case of your battery
operated systems energy is the most
important thing and so sometimes we use
power and energy I mean without making
any distinction but that is not true
actually energy is the and the energy is
very important in battery-operated
systems and essentially we are talking
about reducing energy that is being
drawn by the by the by the portable
system whenever we are discussing about
low powered systems now as I mentioned
we discussed about classification of
sources of power dissipation dynamic
power and the most important component
of this dynamic power is the switching
power and in the last lecture we have
derived the expression for the switching
power dissipation and which is equal to
alpha L where alpha L is the load I mean
load capacity capacitive load alpha L is
the switching activity CL is the load
capacitance VDD is a supply voltage and
F is the frequency of operation so this
is the power dissipation that occurs
because of the because of the
I mean charging and discharging of the
load capacitance and so it is equal to
alpha l clvdd square into F and as you
have seen there are many internal nodes
where also power dissipation occurs and
that can be represented by alpha I dot C
I dot VDD into VDD minus VT
I mean summation of all such different
norms and you may note that here instead
of VDD square there is a ton 3d into VD
minus VT VT the reason for that is you
know for internal nodes the father.the
the supply voltage does not change
between 0 to or L I am infinity actually
when you charge an internal load it can
reach up to VDD minus VT and as a
consequence the equation is little
different from the power dissipation of
the the output capacitive load okay so
with this background now we shall focus
on transition probability in dynamic
circuits we have already discussed about
the switching activity of static CMOS
circuits and we have seen that the
switching the switching activity can be
represented by p 0 to 1 which is equal
to p 0 which is where p 0 is the
probability of remaining the circuit in
with output 0 and p 1 is the probability
for for remaining the circuit in 1 so
from this you can find out the the
switching activity in static CMOS
circuits and we have discussed in detail
how this can be calculated in different
situations and for different types of
gates and then exclusive-or and so on
and also you have discussed about how
the switching activity changes as you
change the Fanning now what about
dynamic CMOS circuits in case of dynamic
CMOS circuits we know that the output is
pre-charged to always output is
pre-charged recharged to
vdd it is always be charged to VDD then
of course during the evaluation phase it
made this discharge to zero or remain
VDD remain output u infinity that means
the output may make a transition from
VDD to 0 or it may remain at VDD so this
is how the dynamic CMOS circuit works
but in such a situation as you can see
always in each I mean for each
computation you have to charge the
output to VDD that means what we can say
that P one probability that the output
will be 1 is always 1 and as a
consequence if you substitute in this
then p 0 to 1 the switching activity
will be equal to p 0 that means since we
are always charged to 1 either it may
make transition to 0 or may not make
transition that's why the switching
activities were equal to the probability
of transition to 0 not the p 0 into p 1
so obviously this switching activity
will be more in dynamic CMOS circuits
because always you are charged with
charging the output to 1 and it may
either discharge or may not discharge
and as a consequence the switching
activity is more as you can see for
different types of gates what is the
switching activity transition activity
for inverter it is 1 by 4 and you may
recall that for static CMOS circuit it
was 1 by 4 not half but 1 by 4 it was
because p 0 was p 0 is half for inverter
the output can may become 0 or 1 and as
a consequence the probability of
becoming 0 is 1/2 probability of
becoming 0 is also 1/2 and as a
consequence p 0 to 1 that is switching
activity was 1 by 4 but in this
particular case for inverter it is equal
to half not 1 by 4 similarly for 2 input
nor gate it is equal to 3 by 4
and because as you know in case of nor
gate probability of becoming the output
zero is three by four record it will
become you know whenever any of our for
nor gate whenever both the inputs are
zero output is one and so whenever any
one of the inputs are zero
I mean one then output is zero and as a
consequence the for two input nor gate
it is three by four and two input NAND
gate it is one by four and in case of
the static CMOS circuits you may recall
that this was equal to 3 by 4 into 1 by
4 so 3 by 16 and for 2 input NAND gate
it was also 3 by 16 that means if we
compare we find that say for inverter
said for static CMOS and say dynamic
CMOS if we compare for inverter it is 1
by 4 for dynamic CMOS it is 1 by 2 for 2
input nor not 2 it is here it is 3 by 16
here it is equal to 3 by 4 for NAND 2
and 2 it is 3 by 16 but here it is equal
to 1 by 4 so we find that the for
dynamic power dynamic CMOS circuits the
switching activity is more but you may
recall that I mentioned that in dynamic
CMOS circuits the overall power
dissipation is less why so the reason
for that is although the switching
activity is more but the overall
capacitance is much less and overall
capacitance is less and secondly you
will see that the output is driving to
one of the capacitors I mean one of the
transistors not both I mean either
similar and most odd P Mo's as a result
the
the load capacitance is also less the
that is that isn't why although
switching activity is more but the the
power dissipation is usually lesser in
dynamic CMOS circuits okay
now another very important aspects of
dynamic CMOS circuits is power
dissipation need to charge yes charge
sharing in case of dynamic gates the
power dissipation takes place due to
phenomenon of charge sharing even when
the output is not zero at the time of
evaluation as we know in static CMOS
circuits power dissipation dynamic power
dissipation occurs only when output
changes from 0 to 1 and 1 to 0 if the
output remains zero in consecutive
computation there will be no dynamic
participation in dynamic CMOS circuits
but unfortunately that is not true in
case of dynamic CMOS circuits so in case
of static CMOS circuits we will find
that power dynamic power dissipation
occurs only when there is our transition
at the output but even when there is no
transition at the output in dynamic CMOS
circuits then there can be dynamic
participation because of charge sharing
how let us let me explain here so this
is a dynamic CMOS gate essentially it is
a three input NAND gate and as you can
see in addition to the output load
capacitance there are three three you
know three nodes three nodes one node is
here another node is here another node
is here the third node there is also a
capacitance here say 3 which is not
mentioned so let us assume that
initially the our input was 1 1 1 so
whenever the input is 1 1 1 then the as
you know the output will be output will
be 0 so the all these capacitors will be
discharged now suppose output input is 1
1 1 0 so whenever you make it 1 1 0
output will switch to 1 so at that time
this
we'll charge to VDD during the
pre-charge phase so what will happen let
me redraw it to explain the operation so
here you have got a PMO's transistor
then there are three and MOS transistors
because it is a and then of course there
is a another transistor here which is
going to take the clock so this is
connected to clock because it is a
dynamic CMOS circuits that is connected
to VDD and these are the three inputs a
B and C so you have got one load
capacitance here CL and here a load
capacitance c1 then another capacitance
C 2 and another capacitance C 3 three
capacitance so initially you have
applied the input 1 1 1 so 1 1 hour
means this V out is 0 the out 1 1 means
how P out is going to 0 now the second
input that means at that time since the
this distance there is on then let me
give the name Q 1 Q 2 and Q 3 all are on
then what will happen
all these capacitors will be discharged
not only CL but C 1 C 2 and C 3 all will
be discharged now suppose the next input
is 1 1 0 that time you know the output
is pre-charged the pre-charge phase
output is pre-charged to VDD now what
will happen during evaluation phase this
is during pre-charge so during
evaluation phase what will happen this
capacitor here the charge is CL into the
charge that has been accumulated is CL
into VDD
so this is 0 this is 1 this is 1 so we
see so what will happen this transistor
is off q3 is off but q1 and q2 these two
are on and as a consequence since this
transistor is on this 10 stars on this
charge will get redistributed in c1 and
c2 and since uglier input was 1 1 1
these two capacitors were discharged
what will happen this charge will get
distributed in c1 and c2 and as a
consequence what will happen the the
output will become will we because of
redistribution the output will we not
VDD say it will attain a new value P new
let's assume because of redistribution
of charge so how do you calculate V new
you can calculate it in the same way
because by considering the conservation
of charge say C 1 plus C 2 C 1 plus C 2
into plus CL into V new this is the new
total charge I mean this is the total
charge that will be equal to CL into VDD
so he new will be equal to will be equal
to CL by C 1 plus C 2 plus CL into VDD
of course here I have not taken into
consideration that this capacitor will
not charge to not will not charge to VDD
but it will charge to VDD minus VTP that
that of course you can take into
consideration that means this will be
here you will be having actually say C 2
into V new my minus here it will be C 2
VT plus C 1 VT these two factors will be
there so this you can take into
consideration while computing but the
main point is output will not be equal
to VDD
but less than VDD it will reduce because
this ferric factor will be more than CL
and then the consequence it will drop
now next time whenever you apply the
same input that will happen again from
Venu it will charge to VDD so next time
you are applying the same input so in
case of static CMOS circuit there will
be no change in the output but in case
of dynamic CMOS circuit it will charge
output will charge from minuto Hidde t
during pre-charge phase and again during
evaluation phase it will be they get
discharged to a new level
that is your Venu so as a consequence
there will be a dynamic power
dissipation and here you can see the
Delta V which is the change in the
voltage is equal to VDD minus CL by C 1
plus C 2 into C 3 into VDD and that
leads to that that makes a difference
and as a consequence this is the power
dissipation that will occur because in
spite of the fact that you have applied
the same input the L there will be some
power dissipation at the output that is
equal to CL into VDD into Delta V that
is CL into C 1 plus C 2 by C 1 plus C 2
plus CL into VDD square so this is a new
component that is only present in
dynamic CMOS circuits that means power
dissipation due to charge sharing can
occur only in dynamic CMOS circuits it
is it does not occur in static CMOS
circuit now having discussed the
switching power dissipation in static
CMOS and dynamic CMOS circuits now let
us take up an example here is an example
where you have got where we have to
realize a function that function is
equal to let's assume function that you
are realizing is equal to function that
you are realizing is equal to F is equal
to it's a or function say A or B or C
me or e or if so it is a six input or
function you are realizing now you can
realize this function in a number of
ways
so first technique can be you will use a
six input nor gate one two three four
five six so a then you will apply b c d
e and f 6 inputs then you will put an
inverter to realize the or function so
this is the first technique of realizing
your six input or function second
alternative is what you can do in the
first stage you will have two nor gates
two nor gates ABC you apply here a b c
and d e f d e and f is applied here then
you will require a two input NAND gate
instead of inverter at the output stage
to realize the function f in all the
cases the function realized is f and
third alternative that you can have is
you can have two input three two input
nor gates in the first stage so a B then
C D then e and F so and then you will
require a three input NAND gate so in
all the three cases you are realizing
the function function so at the time of
what is known as technology mapping you
can choose one of the three
configuration in realizing the function
normally in the standard cell library
you will get inverter you will get two
input NAND and nor gates you will get
three input NAND and nor gates so you
can and also you can have four input
NAND and nor gates and up to six
important and
so whenever you do the realization in
one of the in one of the three ways is
there any difference in area
participation because our main concern
is for participation but you have to
also look into other two parameters
which is power and performance so let us
try to compare the differences in area
performance speed of operation and the
dynamic power rather switching power
that we shall compare for these three
circuits and let us assume we are
realizing in using static signal
circuits so now let us consider to
compute the dynamic power you have to
find out the switching activity so what
will be the switching activity at this
point at this point at this point so
here let me give the name of this node
as output 101 here it is there are two
outputs or one and four to here 301 or
two and oh three internal nodes and
finally you have got define la Cruz now
what is the switching activity at
internal node oh one in the first case
as you know it's a six input nor gate
and as you know the switching activity
will be equal to 60 3 by 4 0 9 6 the
reason for that is it will be you know 1
by 2 to the power 6 into into it will be
63 by 2 to the power 6 so that that
gives you 6 to 3 by 4 0 96 so that will
be the switching activity here and same
switching activity will be taking place
here as well because the number of
transitions that will occur at this
point will be same as the number of
transitions that will occur at this
point because this is a simple inverter
so this is the switching activity now
what will be the switching activity at
this point at this point the switching
TBT will be equal to seven by 64 that we
are getting because it is a three input
nor gate so the switching activity is
equal to 1 by 2 to the power 3 that is
your 16 to 2 by 3 is 8 into 7 by 8 that
makes it 7 by 64 so same will be the
switching activity at at this point
however at this output the switching
activity will be the same 6 to 3 by 4 0
9 6 because these 3 inputs are
considered to be independent assuming
that a b c d e f all are independent and
they have equal probability of becoming
1 and 0 you will get these switching
activities what about this particular
case in this particular case the
switching activity at this point will be
equal to only 3 by 16 that we are
getting from 1 by 4 into 3 by 4 and the
same will be same will be for all the 3
inputs all the 3 points in all the 3
points the switching activity will be 3
by 16
however switching activity here will be
6 to 3 by 4 0 9 6 so from this we
observe that the switching activity of
this particular implementation is much
less at this point 6 to 3 by 4 0 9 6 on
the other hand switching activity is
more at this point and at this point
that is 7 by 64 and here it is still
more 3 by 16 at 3 points so from this
simple observation we may tell that the
switching activity for implementation 3
will be much more compared to
implementation 1 now let us have a
common comparison of this so here I have
taken from some standard cell library
specification you can see the in area
for different cells in part 1 & 2 & 3 &
6 not 2 9 3 are given here relative area
so cell unit is 2 4 for inverter cell
unit is 3 for NAND gate 4 9 3 gate in
the 3 input NAND gate it is 4 16
987 for two input nor gate it is three
and only two three input nor gate it is
two so an input capacitance as you know
who is dependent on the training
so for inverter the input capacitance is
eighty five femto farad and for the two
input NAND gate is is one zero five
femto farad for nad three input NAND
gate is is 132 femto farad for six input
NAND gate is two hundred firm 2 farad
and before nor gate we can see it will
be very close to two input NAND gate so
it is 1 0 1 femto farad the input
capacitance for 3 input nor gate between
capacitance is 1 1 7 and output
capacitance however it will be same
48 Nanofab farad for all of them of
course here we have not this is the
intrinsic output capacitance you may
have some output capacitance because
whenever you are driving a capacitive
load or you are driving some other gates
then of course the load capacitance will
be more and which is expressed by this
expression the average delay will be
dependent on the output capacitance so
for inverter it is point 2 2 plus 1 1
into C 0 for 2 input NAND gate at this
point 3 plus 1 point 2 for C 0 you can
see this this factor is increasing
because of increasing Fanning and for 3
input NAND gate it is point 3 7 plus 1
point 5 5 C 0 into C 0 for 6 input NAND
gate it is 0.65 plus 2 point 3 0 C into
C 0 and 2 input nor gate it is point 2 7
plus 1 point 5 into C 0 so these are the
average delays in nanosecond and for 3
input nor gate it is point 3 1 plus 2
point 0 into C 0 so based on this para
based on these parameters you can
calculate the dynamic power dissipations
of course we are not interested in the
absolute values but we can calculate the
relative values which are shown here the
switching activities I have already
mentioned for the 3 nodes this is for
implementation 1
the switching activities as given here
and for implementation to the switching
activities are given here this p0 and p1
both are given and for our
implementation three these switching
activities are also given here so the
switching activity for different nodes I
have already mentioned these are the
different values of switching activities
so using these switching activities you
can calculate the dynamic power
dissipation and also you can calculate
area and you can calculate delay from
this so here is the comparison for
implementation one area is equal to nine
because you will even requiring one six
input NAND gate and followed by an
inverter so six input nor gate and
inverter actually here it will be an or
gate I mean my mistake I have written
and anyway so it will be nine area is
nine delay is one point one you can
calculate delay for both the gates and
using these equations and you will get
one point one nanosecond and the power
dissipation is equal to six point seven
six point seven power dissipation is
actually switching activity into load
capacitance that has been calculated and
this is the sum of the switching
activity and load capacitances six point
seven in this case and the for the power
dissipation cost is four forty two point
five in the second implementation and
delay is 0.85 an area requirement is 11
because you are live on requiring three
two to three input nor gate followed by
one two input NAND gate so 3 plus 4 into
2 that is 8 plus 3 level that is given
here similarly for the third case you
will require 3 2 input nor gate 3 into 3
9 plus 1 3 input nor gate 9 plus 4 13
area in unit area and delay is 0.87 and
power dissipation cost is 80 2.4 for the
third implementation so from this it is
evident that although the implementation
one is area efficient
delay but delay is more and for
dissipation is less that means
implementation one for implementation
one dynamic participation is less area
required is less all but delay is more
for implementation two we find that area
is more than implementation one delay is
less but the power dissipation is much
higher for implementation three power
dissipation is much larger because of
higher switching activity at the three
nodes we have seen that the switching
activity is much more here for 3 by 3 by
6 3 by 16 3 by 16 3 by 16 and 3 by 16 at
3 nodes these are the 3 nodes here as a
consequence the whenever you go for low
for implementation
obviously the implementation one is more
suitable but whenever you go for minimum
and I mean minimum delay then of course
implementation 2 or implementation 3 is
important so this particular example
clearly demonstrates that you may
realize the same function in different
ways by choosing different cells from
the cell library and that may give you
different area different delay and
different dynamic participation so
depending on your requirement you can
choose you can do the technology mapping
ok so with this example now we shall
come to another important types of power
dissipation we are switching gear to a
new types of circuits that is short
circuit power dissipation and as you
already know short circuit power
dissipation occurs because of slow
change in the input and particularly as
the input is rising changing slowly
either going from 0 to VDD or from VDD
to 0
in the middle portion when the input is
above the more than the threshold
voltage of the N Mo's transistor and
also when it is 15 infinity minus VTP in
this part there is there is a short
circuit between the supply voltage and
ground I have already mentioned about it
and then then there is power dissipation
and that participation we shall compute
now and this is known as short-circuit
power dissipation so here we have taken
an example of an inverter
although an inverter a example has been
taken it can it is applicable to any
CMOS circuit only difference will be
instead of the P Mo's transistor as
pull-up you have a network of P Mo's
transistors in the pull-up and a network
of n MOS transistor has pulled out but
otherwise you know the derivation will
be very similar now let us consider how
the power dissipation is occurring let
me read right so here you have got an
inverter static CMOS inverter this is a
P MOS transistor this is a n MOS
transistor cool down this is VDD and
this is ground okay so you are applying
V in you are getting V out now say
whenever you are after you are changing
the imports let us assume your input is
like this this is your input so output
will have opposite phase
this is the output so this is V this is
V out now here you have got three points
here also three points this is time T 1
when this is time I mean this is the
time T 1 when the input is reaching VT n
that means input is input is going from
0 to VT n this is t1 then the power
power dissipation is starting I mean
they're short circuit is getting
established and it will continue until
your this is your this point is VT n
here and this is the point corresponding
to VDD minus VTP absolute value of VT P
and in between of course you will be
having VDD by 2 point here also I will
have 3 points at t1 t2 and t3 and here
say let's assume t4 middle point is t5
and endpoint is t6 so during this period
conduction is occurring and power
dissipation Locker so if you come if you
draw the current this is your IDs so you
will find that it will be somewhat like
this I have already discussed about this
characteristics so it will start at t1
continue up to t3 and again it will
start with at the t44 it will continue
up to t6 so we shall derive expression
for this current how can you derive it
so first let us calculate the current
what is the mean current that will flow
obviously as you can see this current is
not small is not is not constant it will
it will attain a peak value when the
input is equal to hill D by 2 both the
transistors are in saturation maximum
current will flow then it will mean it
will again it will fall so current is
not constant so what is the average
current that will flow so this is equal
to 2
into 1 by T 1 by T is the period period
means you know in one cycle in one cycle
we'll be having one low to high and
another high to low transition so
accordingly here you will have high to
low and low to high transition so since
they are symmetric let's assume that
both of them are symmetric that means
these two semesters I mean they're
switching characteristics are identical
assuming that we may write 2 into 1 by T
and you can take summation from t1 to t2
I T into DT plus t2 to t3 I T into DT so
this is the this is only for the first
particular first first transition since
for the second transition it will be
same we have we have just multiplied by
2 and then taken the average over a
period of 1 by T now what is I mean
again these two can be assumed to be
same so what we can say that this part
if it is symmetrical that means if we
divide it into two parts t1 to t2 and t2
to t3 again it can you can simplify it
say it will be 4 by T and only t1 to t2
I T DT assuming that all the transitions
are symmetric in the sense that they
follow each of them the it may one may
be me regime in a mirror image of the
other for example in this particular
case this is a mirror image of the other
one but the current that area for both
the both the both the curves will be
identical so we can calculate this now
in this particular case what will be
there I mean that we can calculate this
is equal to 4
i T t1 to t2
what is I what is I T assuming that the
transistor is in saturation because we
know that it is occurring when the input
is above the threshold voltage of the N
Mo's transistor and it is going up to
VDD by 2 so during this period the
transistor will be in saturation so as
you know the expression of our current
is beta by 2 into VDD minus VDD minus VT
n square so we can write beta by 2 into
V in T input is changing minus VT whole
square into DT now what we can do we can
make the substitution V in T is equal to
VDD by tau into T so here what you have
make made one simplification we are
assuming that the input is rising
linearly input is rising linearly so
input is rising linearly so as a
consequence your V in T is equal to VDD
by tau tau is the rise time and at any
at at any instant it will be the voltage
will be equal to 50 by tau into 50 so in
time tau it will reach VDD so at any at
any instant of time T it will be equal
to VDD by tau into T so we can
substitute this here and this will
become equal to and okay you can make
some more substitutions so here T what
will be the value of T 1 if we
substitute T 1 then it will be equal to
tau by tau by VDD into VT as we know
when the input is equal to VT then it is
then the time is T 1 so it is tau by V
into
similarly 42 it will be equal to t2 will
be equal to vdd by 2 so T 2 will be
equal to tau by 2 because V DD will be
become V DD by VT by 50 will be equal to
50 by 2 so VD VD will cancel it will be
equal to tau by 2 so this you can
substitute in this expression so after
substitution what we shall get is I mean
is equal to 2 beta by 2 then it is equal
to T by VDD into VT and here it will be
tau by 2 so you have substituted in
place of T 1 tau by filled into VT and
for T 2 tau by 2 and here it will be
equal to VDD by tau into t minus V T
into DT of course here they will be a
square now again we substitute again we
substitute VDD by tau into T is equal to
sorry minus VT is equal to X then VDD by
tau into DT if we differentiate that
will be equal to DX so this if we
substitute here what we shall get here
by substituting this it will become I
mean is equal to 2 beta by T 2 beta by T
so this is T into sorry it was it was 2
only so that has come from this
expression 2 bit about our that average
value will be earlier it was okay so it
will be 250 so 2 beta by T into
here it will go from 0 0 to VDD minus bi
to minus VT X square so this is this is
X we have substituted and this is DX
into of course this factor will be there
tau by tau by VDD so then this will be
equal to 2 beta by T into tau by VDD
into X square X cube by 3 by after
integration so if we substitute X what
we shall get after substituting X we
shall get this is I mean will be equal
to 2 beta by T into tau by 24 VDD into
VDD minus 2 VT whole cube or you can
submit simplifies beta by 12 VDD into
VDD we have can United's
to VT whole cube into tau by T now this
is the current so the power dissipation
will be equal to P short circuit will be
equal to VDD into I mean that will be
equal to beta by 12 into this VDD will
cancel with this VDD so we shall get VDD
minus 2 V T cube into tau by T or this T
can be written as if anyway so this is
the expression so this we can write into
if instead of tau so what what does this
expression tell us this expression tells
us that the source short-circuit power
dissipation is proportional to the
currency of operation if it is
proportional to the rise and fall time
that is the transition time it is
proportional to V D minus 250 Q it is
dependent on the supply voltage and also
it is dependent on beta you know in in
beta we have the parameter that is
mobility of electron then we have the
parameter width of the transistor length
of the transistors so the short-circuit
power dissipation is dependent on the
physical dimension of the transistors
mobility of electrons and holes the
transition time rise and fall time of
the input and the frequency of operation
and of course lot last but not the least
component is the supply voltage because
there is a factor of VDD minus VT a 2 VT
and cube so this is the short circuit
power dissipation expression and
obviously this expression this
particular current is significant in
some circuits when the input is changing
slowly now as the supply voltage is
reduced what impact it has got on this
short circuit power dissipation so here
I am explained the transfer
characteristic for different supply
voltages as you can see the as the
supply voltage is reduced from 5 volt to
4 volt as you mean VT n is equal to 1
volt and VT B is equal to minus 1 volt
we can see the characteristic curves
will change and the the region of such
circuit participation is also getting
changed and when we are reaching when we
are reaching the point VDD VDD is equal
to VT n plus absolute value of VT P at
that point what will happen at that
point as we know the transfer
characteristic will be somewhat like
this
and this is the point where you have got
vtm and also this is equal to absolute
variable hello BTP this is the point and
of course this is VDD so at this point
we find there is no there is no slow
transition that means this is VDD and
here it is VDD and when the transition
is occurring in the middle there it is
changing abruptly and there is no
current flow through the circuit because
as at that point the initially the n MOS
transistor is on n MOS sorry this is P
Mo's transistor is on and here n MOS on
so there is no point where both the
transistor is on and as a consequence
what will happen there is no such
circuit power dissipation so you may say
that why not use a supply voltage which
is equal to VT n plus VT P absolute
value of VT P but unfortunately if you
do that then you will see that delay
will increase delay will be very high so
although this is a way of reducing the
short-circuit power dissipation but this
that technique cannot be used because of
high delay of the circuit and another
situation is when the input voltage is
less than this that means if the input
voltage is whenever VDD is less than VT
n plus VT P will the circuit operate in
this particular case yes the circuit
will operate but the transfer
characteristic will have a a kind of
hysteresis as you can see when the input
is increasing it is going from say
initially the output is VDD then at this
point the PMO's transistor is turning
off and during this period since the
output is already charged to VDD it
continues and
this point when the N Mo's transistor is
done
I mean turning on and output is brought
down to zero and then it is going to VDD
on the other hand when it is reading on
the when it is reduced from VDD to input
is reduced from three to zero you can
see it will follow this part so the
initially the N Mo's transistor will
remain on and it will remain on up to
this point and then it will continue and
the output will remain continued to be
zero because output
none of the transistors are on during
this period and at this point where
affinity minus VTP absolute value of ATP
again it will rise to VDD because the
PMO's transistor will turn on so we find
that during this period none of the
transistors are on so they between this
VDD minus VTP 250 n so during this part
of the card none of the 10 stirs are on
and you will get a kind of hysteresis if
you draw the transfer techni still get
the hysteresis so circuit will offer it
but you will find that delay will be
very high the reason for that is you can
see finally while in the input is
increasing only for this part P Mo's
transistor is on and during this part
none of the transistor is on similarly
while when the input is reduced from VDD
to 0 during this period the N Mo's
transistor is on up to this point and
ending this period none of the
transistors are on and then again we
have P Mo's transistor is turning on to
bring it to 1 so delay will be very
large okay now how this short circuit
power dissipation changes as you change
the the rise and fall energy that the
transition time of the input that means
the value of tau we have seen that there
is a dependence linear dependence on the
value of tau so here you can see so how
the short-circuit power dissipation will
change you can see we have plotted for
three different values of tau 1
nanosecond to nanosecond and thin a 5
nanoseconds
obviously when the rise time and fall
time is called 5min a second that time
we find that this area is much larger
that means they say in this particular
the area that will covered by this
triangle will be much higher than when
it is tau is equal to 100 seconds so
this is the current that will flow for
different rise
I mean rise and fall time of the input
signal so this this source how the power
dissipation will change as you change
the rise and fall time and that is the
reason why we insert buffers at regular
interval in a circuit so that the rise
and fall times are not very high I mean
this would be recapped within certain
limit coming to a third important aspect
you can see we have short-circuit power
dissipation for different load
capacitance so initially the load
capacitance is zero and then we have
increased the load capacitance and you
can see the it is the cab is going down
because it will not charge to a higher
level but it did that it will it will
that it will go down and as a
consequence the current that will flow
will be smaller and the area that will
be closed by this rectangle by this
triangle will be less that means when
the load capacitance is increased the
short circuit power dissipation gets
reduced however the the although the
short circuit power dissipation reduces
the delay will increase because of
increased capacitance so from this
discussion what conclusion we can make
so far as the short circuit
participation is concerned there are
then we have seen there are three
important parameters which you can
control one is frequency of operations
but we cannot usually compromise on
performance that's the reason why we
cannot really reduce frequency to reduce
participation however we can reduce Tao
we can also reduce the parameter that is
your sometimes we can reduce the load
capacitance and node capacitance can be
increased to reduce the short circuit
participation and of course the supply
voltage scaling
reduction of the supply voltage is the
most important parameter I mean
important parameter that can be used to
reduce the short circuit participation
so with this we shall we have come to
the end of today's lecture in the next
lecture we shall primarily discuss about
the leakage power dissipation but before
that we shall also discuss about the
dynamic power dissipation due to
glitching there is another power
dissipation that is known as glitching
power dissipation that we shall discuss
in the next lecture
thank you
dynamic power dissipation we have
started our discussion on various
sources of power dissipation in CMOS
circuits in the last lecture and I have
mentioned about two different types of
power dissipations whether you can
categorize the social support
dissipation into two types dynamic and
Static and in the last lecture I have
introduced the switching power
dissipation which is one of the
components of dynamic power dissipation
and today we shall continue our
discussion on switching power
dissipation and then as you shall see
later on I shall discuss about the short
circuit power dissipation which is
another component of dynamic power
dissipation so here is the agenda of
today's lecture essentially I shall
briefly recapitulate about the types of
power dissipation then classification of
sources of power dissipation as I
mentioned we are focusing on dynamic
power in this lecture I have already
started discussion on switching power
dissipation and it will be followed by
short circuit power dissipation and
glitching power dissipation and later on
I shall discuss about the degrees of
freedom that means what are the
parameters you can use to reduce dynamic
power dissipation rather what is your
handle in reducing the power dissipation
we have discussed about three types of
power in my last lecture peak power
average power and this definition
difference between power and energy as
you know peak power is very important
because at any instant of time what is
the maximum power that is being that is
taken that is drawn by the
circuit in operation is very important
for reliable operation of the circuit
and as you know because of the peak
power there is transience on the
powerlines and that may lead to glitch
and error in the signal we are not going
to discuss in detail today similarly the
average power is important particularly
for battery operated embedded systems
battery operated portable systems where
the life of the system depends on the
battery battery and how long the battery
can sustain the power and on the average
how much power dissipation is taking
place that is very important that's why
most of our discussion will be based on
this average power dissipation and I
have mentioned about the difference
between power and energy as we shall see
actually in case of your battery
operated systems energy is the most
important thing and so sometimes we use
power and energy I mean without making
any distinction but that is not true
actually energy is the and the energy is
very important in battery-operated
systems and essentially we are talking
about reducing energy that is being
drawn by the by the by the portable
system whenever we are discussing about
low powered systems now as I mentioned
we discussed about classification of
sources of power dissipation dynamic
power and the most important component
of this dynamic power is the switching
power and in the last lecture we have
derived the expression for the switching
power dissipation and which is equal to
alpha L where alpha L is the load I mean
load capacity capacitive load alpha L is
the switching activity CL is the load
capacitance VDD is a supply voltage and
F is the frequency of operation so this
is the power dissipation that occurs
because of the because of the
I mean charging and discharging of the
load capacitance and so it is equal to
alpha l clvdd square into F and as you
have seen there are many internal nodes
where also power dissipation occurs and
that can be represented by alpha I dot C
I dot VDD into VDD minus VT
I mean summation of all such different
norms and you may note that here instead
of VDD square there is a ton 3d into VD
minus VT VT the reason for that is you
know for internal nodes the father.the
the supply voltage does not change
between 0 to or L I am infinity actually
when you charge an internal load it can
reach up to VDD minus VT and as a
consequence the equation is little
different from the power dissipation of
the the output capacitive load okay so
with this background now we shall focus
on transition probability in dynamic
circuits we have already discussed about
the switching activity of static CMOS
circuits and we have seen that the
switching the switching activity can be
represented by p 0 to 1 which is equal
to p 0 which is where p 0 is the
probability of remaining the circuit in
with output 0 and p 1 is the probability
for for remaining the circuit in 1 so
from this you can find out the the
switching activity in static CMOS
circuits and we have discussed in detail
how this can be calculated in different
situations and for different types of
gates and then exclusive-or and so on
and also you have discussed about how
the switching activity changes as you
change the Fanning now what about
dynamic CMOS circuits in case of dynamic
CMOS circuits we know that the output is
pre-charged to always output is
pre-charged recharged to
vdd it is always be charged to VDD then
of course during the evaluation phase it
made this discharge to zero or remain
VDD remain output u infinity that means
the output may make a transition from
VDD to 0 or it may remain at VDD so this
is how the dynamic CMOS circuit works
but in such a situation as you can see
always in each I mean for each
computation you have to charge the
output to VDD that means what we can say
that P one probability that the output
will be 1 is always 1 and as a
consequence if you substitute in this
then p 0 to 1 the switching activity
will be equal to p 0 that means since we
are always charged to 1 either it may
make transition to 0 or may not make
transition that's why the switching
activities were equal to the probability
of transition to 0 not the p 0 into p 1
so obviously this switching activity
will be more in dynamic CMOS circuits
because always you are charged with
charging the output to 1 and it may
either discharge or may not discharge
and as a consequence the switching
activity is more as you can see for
different types of gates what is the
switching activity transition activity
for inverter it is 1 by 4 and you may
recall that for static CMOS circuit it
was 1 by 4 not half but 1 by 4 it was
because p 0 was p 0 is half for inverter
the output can may become 0 or 1 and as
a consequence the probability of
becoming 0 is 1/2 probability of
becoming 0 is also 1/2 and as a
consequence p 0 to 1 that is switching
activity was 1 by 4 but in this
particular case for inverter it is equal
to half not 1 by 4 similarly for 2 input
nor gate it is equal to 3 by 4
and because as you know in case of nor
gate probability of becoming the output
zero is three by four record it will
become you know whenever any of our for
nor gate whenever both the inputs are
zero output is one and so whenever any
one of the inputs are zero
I mean one then output is zero and as a
consequence the for two input nor gate
it is three by four and two input NAND
gate it is one by four and in case of
the static CMOS circuits you may recall
that this was equal to 3 by 4 into 1 by
4 so 3 by 16 and for 2 input NAND gate
it was also 3 by 16 that means if we
compare we find that say for inverter
said for static CMOS and say dynamic
CMOS if we compare for inverter it is 1
by 4 for dynamic CMOS it is 1 by 2 for 2
input nor not 2 it is here it is 3 by 16
here it is equal to 3 by 4 for NAND 2
and 2 it is 3 by 16 but here it is equal
to 1 by 4 so we find that the for
dynamic power dynamic CMOS circuits the
switching activity is more but you may
recall that I mentioned that in dynamic
CMOS circuits the overall power
dissipation is less why so the reason
for that is although the switching
activity is more but the overall
capacitance is much less and overall
capacitance is less and secondly you
will see that the output is driving to
one of the capacitors I mean one of the
transistors not both I mean either
similar and most odd P Mo's as a result
the
the load capacitance is also less the
that is that isn't why although
switching activity is more but the the
power dissipation is usually lesser in
dynamic CMOS circuits okay
now another very important aspects of
dynamic CMOS circuits is power
dissipation need to charge yes charge
sharing in case of dynamic gates the
power dissipation takes place due to
phenomenon of charge sharing even when
the output is not zero at the time of
evaluation as we know in static CMOS
circuits power dissipation dynamic power
dissipation occurs only when output
changes from 0 to 1 and 1 to 0 if the
output remains zero in consecutive
computation there will be no dynamic
participation in dynamic CMOS circuits
but unfortunately that is not true in
case of dynamic CMOS circuits so in case
of static CMOS circuits we will find
that power dynamic power dissipation
occurs only when there is our transition
at the output but even when there is no
transition at the output in dynamic CMOS
circuits then there can be dynamic
participation because of charge sharing
how let us let me explain here so this
is a dynamic CMOS gate essentially it is
a three input NAND gate and as you can
see in addition to the output load
capacitance there are three three you
know three nodes three nodes one node is
here another node is here another node
is here the third node there is also a
capacitance here say 3 which is not
mentioned so let us assume that
initially the our input was 1 1 1 so
whenever the input is 1 1 1 then the as
you know the output will be output will
be 0 so the all these capacitors will be
discharged now suppose output input is 1
1 1 0 so whenever you make it 1 1 0
output will switch to 1 so at that time
this
we'll charge to VDD during the
pre-charge phase so what will happen let
me redraw it to explain the operation so
here you have got a PMO's transistor
then there are three and MOS transistors
because it is a and then of course there
is a another transistor here which is
going to take the clock so this is
connected to clock because it is a
dynamic CMOS circuits that is connected
to VDD and these are the three inputs a
B and C so you have got one load
capacitance here CL and here a load
capacitance c1 then another capacitance
C 2 and another capacitance C 3 three
capacitance so initially you have
applied the input 1 1 1 so 1 1 hour
means this V out is 0 the out 1 1 means
how P out is going to 0 now the second
input that means at that time since the
this distance there is on then let me
give the name Q 1 Q 2 and Q 3 all are on
then what will happen
all these capacitors will be discharged
not only CL but C 1 C 2 and C 3 all will
be discharged now suppose the next input
is 1 1 0 that time you know the output
is pre-charged the pre-charge phase
output is pre-charged to VDD now what
will happen during evaluation phase this
is during pre-charge so during
evaluation phase what will happen this
capacitor here the charge is CL into the
charge that has been accumulated is CL
into VDD
so this is 0 this is 1 this is 1 so we
see so what will happen this transistor
is off q3 is off but q1 and q2 these two
are on and as a consequence since this
transistor is on this 10 stars on this
charge will get redistributed in c1 and
c2 and since uglier input was 1 1 1
these two capacitors were discharged
what will happen this charge will get
distributed in c1 and c2 and as a
consequence what will happen the the
output will become will we because of
redistribution the output will we not
VDD say it will attain a new value P new
let's assume because of redistribution
of charge so how do you calculate V new
you can calculate it in the same way
because by considering the conservation
of charge say C 1 plus C 2 C 1 plus C 2
into plus CL into V new this is the new
total charge I mean this is the total
charge that will be equal to CL into VDD
so he new will be equal to will be equal
to CL by C 1 plus C 2 plus CL into VDD
of course here I have not taken into
consideration that this capacitor will
not charge to not will not charge to VDD
but it will charge to VDD minus VTP that
that of course you can take into
consideration that means this will be
here you will be having actually say C 2
into V new my minus here it will be C 2
VT plus C 1 VT these two factors will be
there so this you can take into
consideration while computing but the
main point is output will not be equal
to VDD
but less than VDD it will reduce because
this ferric factor will be more than CL
and then the consequence it will drop
now next time whenever you apply the
same input that will happen again from
Venu it will charge to VDD so next time
you are applying the same input so in
case of static CMOS circuit there will
be no change in the output but in case
of dynamic CMOS circuit it will charge
output will charge from minuto Hidde t
during pre-charge phase and again during
evaluation phase it will be they get
discharged to a new level
that is your Venu so as a consequence
there will be a dynamic power
dissipation and here you can see the
Delta V which is the change in the
voltage is equal to VDD minus CL by C 1
plus C 2 into C 3 into VDD and that
leads to that that makes a difference
and as a consequence this is the power
dissipation that will occur because in
spite of the fact that you have applied
the same input the L there will be some
power dissipation at the output that is
equal to CL into VDD into Delta V that
is CL into C 1 plus C 2 by C 1 plus C 2
plus CL into VDD square so this is a new
component that is only present in
dynamic CMOS circuits that means power
dissipation due to charge sharing can
occur only in dynamic CMOS circuits it
is it does not occur in static CMOS
circuit now having discussed the
switching power dissipation in static
CMOS and dynamic CMOS circuits now let
us take up an example here is an example
where you have got where we have to
realize a function that function is
equal to let's assume function that you
are realizing is equal to function that
you are realizing is equal to F is equal
to it's a or function say A or B or C
me or e or if so it is a six input or
function you are realizing now you can
realize this function in a number of
ways
so first technique can be you will use a
six input nor gate one two three four
five six so a then you will apply b c d
e and f 6 inputs then you will put an
inverter to realize the or function so
this is the first technique of realizing
your six input or function second
alternative is what you can do in the
first stage you will have two nor gates
two nor gates ABC you apply here a b c
and d e f d e and f is applied here then
you will require a two input NAND gate
instead of inverter at the output stage
to realize the function f in all the
cases the function realized is f and
third alternative that you can have is
you can have two input three two input
nor gates in the first stage so a B then
C D then e and F so and then you will
require a three input NAND gate so in
all the three cases you are realizing
the function function so at the time of
what is known as technology mapping you
can choose one of the three
configuration in realizing the function
normally in the standard cell library
you will get inverter you will get two
input NAND and nor gates you will get
three input NAND and nor gates so you
can and also you can have four input
NAND and nor gates and up to six
important and
so whenever you do the realization in
one of the in one of the three ways is
there any difference in area
participation because our main concern
is for participation but you have to
also look into other two parameters
which is power and performance so let us
try to compare the differences in area
performance speed of operation and the
dynamic power rather switching power
that we shall compare for these three
circuits and let us assume we are
realizing in using static signal
circuits so now let us consider to
compute the dynamic power you have to
find out the switching activity so what
will be the switching activity at this
point at this point at this point so
here let me give the name of this node
as output 101 here it is there are two
outputs or one and four to here 301 or
two and oh three internal nodes and
finally you have got define la Cruz now
what is the switching activity at
internal node oh one in the first case
as you know it's a six input nor gate
and as you know the switching activity
will be equal to 60 3 by 4 0 9 6 the
reason for that is it will be you know 1
by 2 to the power 6 into into it will be
63 by 2 to the power 6 so that that
gives you 6 to 3 by 4 0 96 so that will
be the switching activity here and same
switching activity will be taking place
here as well because the number of
transitions that will occur at this
point will be same as the number of
transitions that will occur at this
point because this is a simple inverter
so this is the switching activity now
what will be the switching activity at
this point at this point the switching
TBT will be equal to seven by 64 that we
are getting because it is a three input
nor gate so the switching activity is
equal to 1 by 2 to the power 3 that is
your 16 to 2 by 3 is 8 into 7 by 8 that
makes it 7 by 64 so same will be the
switching activity at at this point
however at this output the switching
activity will be the same 6 to 3 by 4 0
9 6 because these 3 inputs are
considered to be independent assuming
that a b c d e f all are independent and
they have equal probability of becoming
1 and 0 you will get these switching
activities what about this particular
case in this particular case the
switching activity at this point will be
equal to only 3 by 16 that we are
getting from 1 by 4 into 3 by 4 and the
same will be same will be for all the 3
inputs all the 3 points in all the 3
points the switching activity will be 3
by 16
however switching activity here will be
6 to 3 by 4 0 9 6 so from this we
observe that the switching activity of
this particular implementation is much
less at this point 6 to 3 by 4 0 9 6 on
the other hand switching activity is
more at this point and at this point
that is 7 by 64 and here it is still
more 3 by 16 at 3 points so from this
simple observation we may tell that the
switching activity for implementation 3
will be much more compared to
implementation 1 now let us have a
common comparison of this so here I have
taken from some standard cell library
specification you can see the in area
for different cells in part 1 & 2 & 3 &
6 not 2 9 3 are given here relative area
so cell unit is 2 4 for inverter cell
unit is 3 for NAND gate 4 9 3 gate in
the 3 input NAND gate it is 4 16
987 for two input nor gate it is three
and only two three input nor gate it is
two so an input capacitance as you know
who is dependent on the training
so for inverter the input capacitance is
eighty five femto farad and for the two
input NAND gate is is one zero five
femto farad for nad three input NAND
gate is is 132 femto farad for six input
NAND gate is two hundred firm 2 farad
and before nor gate we can see it will
be very close to two input NAND gate so
it is 1 0 1 femto farad the input
capacitance for 3 input nor gate between
capacitance is 1 1 7 and output
capacitance however it will be same
48 Nanofab farad for all of them of
course here we have not this is the
intrinsic output capacitance you may
have some output capacitance because
whenever you are driving a capacitive
load or you are driving some other gates
then of course the load capacitance will
be more and which is expressed by this
expression the average delay will be
dependent on the output capacitance so
for inverter it is point 2 2 plus 1 1
into C 0 for 2 input NAND gate at this
point 3 plus 1 point 2 for C 0 you can
see this this factor is increasing
because of increasing Fanning and for 3
input NAND gate it is point 3 7 plus 1
point 5 5 C 0 into C 0 for 6 input NAND
gate it is 0.65 plus 2 point 3 0 C into
C 0 and 2 input nor gate it is point 2 7
plus 1 point 5 into C 0 so these are the
average delays in nanosecond and for 3
input nor gate it is point 3 1 plus 2
point 0 into C 0 so based on this para
based on these parameters you can
calculate the dynamic power dissipations
of course we are not interested in the
absolute values but we can calculate the
relative values which are shown here the
switching activities I have already
mentioned for the 3 nodes this is for
implementation 1
the switching activities as given here
and for implementation to the switching
activities are given here this p0 and p1
both are given and for our
implementation three these switching
activities are also given here so the
switching activity for different nodes I
have already mentioned these are the
different values of switching activities
so using these switching activities you
can calculate the dynamic power
dissipation and also you can calculate
area and you can calculate delay from
this so here is the comparison for
implementation one area is equal to nine
because you will even requiring one six
input NAND gate and followed by an
inverter so six input nor gate and
inverter actually here it will be an or
gate I mean my mistake I have written
and anyway so it will be nine area is
nine delay is one point one you can
calculate delay for both the gates and
using these equations and you will get
one point one nanosecond and the power
dissipation is equal to six point seven
six point seven power dissipation is
actually switching activity into load
capacitance that has been calculated and
this is the sum of the switching
activity and load capacitances six point
seven in this case and the for the power
dissipation cost is four forty two point
five in the second implementation and
delay is 0.85 an area requirement is 11
because you are live on requiring three
two to three input nor gate followed by
one two input NAND gate so 3 plus 4 into
2 that is 8 plus 3 level that is given
here similarly for the third case you
will require 3 2 input nor gate 3 into 3
9 plus 1 3 input nor gate 9 plus 4 13
area in unit area and delay is 0.87 and
power dissipation cost is 80 2.4 for the
third implementation so from this it is
evident that although the implementation
one is area efficient
delay but delay is more and for
dissipation is less that means
implementation one for implementation
one dynamic participation is less area
required is less all but delay is more
for implementation two we find that area
is more than implementation one delay is
less but the power dissipation is much
higher for implementation three power
dissipation is much larger because of
higher switching activity at the three
nodes we have seen that the switching
activity is much more here for 3 by 3 by
6 3 by 16 3 by 16 3 by 16 and 3 by 16 at
3 nodes these are the 3 nodes here as a
consequence the whenever you go for low
for implementation
obviously the implementation one is more
suitable but whenever you go for minimum
and I mean minimum delay then of course
implementation 2 or implementation 3 is
important so this particular example
clearly demonstrates that you may
realize the same function in different
ways by choosing different cells from
the cell library and that may give you
different area different delay and
different dynamic participation so
depending on your requirement you can
choose you can do the technology mapping
ok so with this example now we shall
come to another important types of power
dissipation we are switching gear to a
new types of circuits that is short
circuit power dissipation and as you
already know short circuit power
dissipation occurs because of slow
change in the input and particularly as
the input is rising changing slowly
either going from 0 to VDD or from VDD
to 0
in the middle portion when the input is
above the more than the threshold
voltage of the N Mo's transistor and
also when it is 15 infinity minus VTP in
this part there is there is a short
circuit between the supply voltage and
ground I have already mentioned about it
and then then there is power dissipation
and that participation we shall compute
now and this is known as short-circuit
power dissipation so here we have taken
an example of an inverter
although an inverter a example has been
taken it can it is applicable to any
CMOS circuit only difference will be
instead of the P Mo's transistor as
pull-up you have a network of P Mo's
transistors in the pull-up and a network
of n MOS transistor has pulled out but
otherwise you know the derivation will
be very similar now let us consider how
the power dissipation is occurring let
me read right so here you have got an
inverter static CMOS inverter this is a
P MOS transistor this is a n MOS
transistor cool down this is VDD and
this is ground okay so you are applying
V in you are getting V out now say
whenever you are after you are changing
the imports let us assume your input is
like this this is your input so output
will have opposite phase
this is the output so this is V this is
V out now here you have got three points
here also three points this is time T 1
when this is time I mean this is the
time T 1 when the input is reaching VT n
that means input is input is going from
0 to VT n this is t1 then the power
power dissipation is starting I mean
they're short circuit is getting
established and it will continue until
your this is your this point is VT n
here and this is the point corresponding
to VDD minus VTP absolute value of VT P
and in between of course you will be
having VDD by 2 point here also I will
have 3 points at t1 t2 and t3 and here
say let's assume t4 middle point is t5
and endpoint is t6 so during this period
conduction is occurring and power
dissipation Locker so if you come if you
draw the current this is your IDs so you
will find that it will be somewhat like
this I have already discussed about this
characteristics so it will start at t1
continue up to t3 and again it will
start with at the t44 it will continue
up to t6 so we shall derive expression
for this current how can you derive it
so first let us calculate the current
what is the mean current that will flow
obviously as you can see this current is
not small is not is not constant it will
it will attain a peak value when the
input is equal to hill D by 2 both the
transistors are in saturation maximum
current will flow then it will mean it
will again it will fall so current is
not constant so what is the average
current that will flow so this is equal
to 2
into 1 by T 1 by T is the period period
means you know in one cycle in one cycle
we'll be having one low to high and
another high to low transition so
accordingly here you will have high to
low and low to high transition so since
they are symmetric let's assume that
both of them are symmetric that means
these two semesters I mean they're
switching characteristics are identical
assuming that we may write 2 into 1 by T
and you can take summation from t1 to t2
I T into DT plus t2 to t3 I T into DT so
this is the this is only for the first
particular first first transition since
for the second transition it will be
same we have we have just multiplied by
2 and then taken the average over a
period of 1 by T now what is I mean
again these two can be assumed to be
same so what we can say that this part
if it is symmetrical that means if we
divide it into two parts t1 to t2 and t2
to t3 again it can you can simplify it
say it will be 4 by T and only t1 to t2
I T DT assuming that all the transitions
are symmetric in the sense that they
follow each of them the it may one may
be me regime in a mirror image of the
other for example in this particular
case this is a mirror image of the other
one but the current that area for both
the both the both the curves will be
identical so we can calculate this now
in this particular case what will be
there I mean that we can calculate this
is equal to 4
i T t1 to t2
what is I what is I T assuming that the
transistor is in saturation because we
know that it is occurring when the input
is above the threshold voltage of the N
Mo's transistor and it is going up to
VDD by 2 so during this period the
transistor will be in saturation so as
you know the expression of our current
is beta by 2 into VDD minus VDD minus VT
n square so we can write beta by 2 into
V in T input is changing minus VT whole
square into DT now what we can do we can
make the substitution V in T is equal to
VDD by tau into T so here what you have
make made one simplification we are
assuming that the input is rising
linearly input is rising linearly so
input is rising linearly so as a
consequence your V in T is equal to VDD
by tau tau is the rise time and at any
at at any instant it will be the voltage
will be equal to 50 by tau into 50 so in
time tau it will reach VDD so at any at
any instant of time T it will be equal
to VDD by tau into T so we can
substitute this here and this will
become equal to and okay you can make
some more substitutions so here T what
will be the value of T 1 if we
substitute T 1 then it will be equal to
tau by tau by VDD into VT as we know
when the input is equal to VT then it is
then the time is T 1 so it is tau by V
into
similarly 42 it will be equal to t2 will
be equal to vdd by 2 so T 2 will be
equal to tau by 2 because V DD will be
become V DD by VT by 50 will be equal to
50 by 2 so VD VD will cancel it will be
equal to tau by 2 so this you can
substitute in this expression so after
substitution what we shall get is I mean
is equal to 2 beta by 2 then it is equal
to T by VDD into VT and here it will be
tau by 2 so you have substituted in
place of T 1 tau by filled into VT and
for T 2 tau by 2 and here it will be
equal to VDD by tau into t minus V T
into DT of course here they will be a
square now again we substitute again we
substitute VDD by tau into T is equal to
sorry minus VT is equal to X then VDD by
tau into DT if we differentiate that
will be equal to DX so this if we
substitute here what we shall get here
by substituting this it will become I
mean is equal to 2 beta by T 2 beta by T
so this is T into sorry it was it was 2
only so that has come from this
expression 2 bit about our that average
value will be earlier it was okay so it
will be 250 so 2 beta by T into
here it will go from 0 0 to VDD minus bi
to minus VT X square so this is this is
X we have substituted and this is DX
into of course this factor will be there
tau by tau by VDD so then this will be
equal to 2 beta by T into tau by VDD
into X square X cube by 3 by after
integration so if we substitute X what
we shall get after substituting X we
shall get this is I mean will be equal
to 2 beta by T into tau by 24 VDD into
VDD minus 2 VT whole cube or you can
submit simplifies beta by 12 VDD into
VDD we have can United's
to VT whole cube into tau by T now this
is the current so the power dissipation
will be equal to P short circuit will be
equal to VDD into I mean that will be
equal to beta by 12 into this VDD will
cancel with this VDD so we shall get VDD
minus 2 V T cube into tau by T or this T
can be written as if anyway so this is
the expression so this we can write into
if instead of tau so what what does this
expression tell us this expression tells
us that the source short-circuit power
dissipation is proportional to the
currency of operation if it is
proportional to the rise and fall time
that is the transition time it is
proportional to V D minus 250 Q it is
dependent on the supply voltage and also
it is dependent on beta you know in in
beta we have the parameter that is
mobility of electron then we have the
parameter width of the transistor length
of the transistors so the short-circuit
power dissipation is dependent on the
physical dimension of the transistors
mobility of electrons and holes the
transition time rise and fall time of
the input and the frequency of operation
and of course lot last but not the least
component is the supply voltage because
there is a factor of VDD minus VT a 2 VT
and cube so this is the short circuit
power dissipation expression and
obviously this expression this
particular current is significant in
some circuits when the input is changing
slowly now as the supply voltage is
reduced what impact it has got on this
short circuit power dissipation so here
I am explained the transfer
characteristic for different supply
voltages as you can see the as the
supply voltage is reduced from 5 volt to
4 volt as you mean VT n is equal to 1
volt and VT B is equal to minus 1 volt
we can see the characteristic curves
will change and the the region of such
circuit participation is also getting
changed and when we are reaching when we
are reaching the point VDD VDD is equal
to VT n plus absolute value of VT P at
that point what will happen at that
point as we know the transfer
characteristic will be somewhat like
this
and this is the point where you have got
vtm and also this is equal to absolute
variable hello BTP this is the point and
of course this is VDD so at this point
we find there is no there is no slow
transition that means this is VDD and
here it is VDD and when the transition
is occurring in the middle there it is
changing abruptly and there is no
current flow through the circuit because
as at that point the initially the n MOS
transistor is on n MOS sorry this is P
Mo's transistor is on and here n MOS on
so there is no point where both the
transistor is on and as a consequence
what will happen there is no such
circuit power dissipation so you may say
that why not use a supply voltage which
is equal to VT n plus VT P absolute
value of VT P but unfortunately if you
do that then you will see that delay
will increase delay will be very high so
although this is a way of reducing the
short-circuit power dissipation but this
that technique cannot be used because of
high delay of the circuit and another
situation is when the input voltage is
less than this that means if the input
voltage is whenever VDD is less than VT
n plus VT P will the circuit operate in
this particular case yes the circuit
will operate but the transfer
characteristic will have a a kind of
hysteresis as you can see when the input
is increasing it is going from say
initially the output is VDD then at this
point the PMO's transistor is turning
off and during this period since the
output is already charged to VDD it
continues and
this point when the N Mo's transistor is
done
I mean turning on and output is brought
down to zero and then it is going to VDD
on the other hand when it is reading on
the when it is reduced from VDD to input
is reduced from three to zero you can
see it will follow this part so the
initially the N Mo's transistor will
remain on and it will remain on up to
this point and then it will continue and
the output will remain continued to be
zero because output
none of the transistors are on during
this period and at this point where
affinity minus VTP absolute value of ATP
again it will rise to VDD because the
PMO's transistor will turn on so we find
that during this period none of the
transistors are on so they between this
VDD minus VTP 250 n so during this part
of the card none of the 10 stirs are on
and you will get a kind of hysteresis if
you draw the transfer techni still get
the hysteresis so circuit will offer it
but you will find that delay will be
very high the reason for that is you can
see finally while in the input is
increasing only for this part P Mo's
transistor is on and during this part
none of the transistor is on similarly
while when the input is reduced from VDD
to 0 during this period the N Mo's
transistor is on up to this point and
ending this period none of the
transistors are on and then again we
have P Mo's transistor is turning on to
bring it to 1 so delay will be very
large okay now how this short circuit
power dissipation changes as you change
the the rise and fall energy that the
transition time of the input that means
the value of tau we have seen that there
is a dependence linear dependence on the
value of tau so here you can see so how
the short-circuit power dissipation will
change you can see we have plotted for
three different values of tau 1
nanosecond to nanosecond and thin a 5
nanoseconds
obviously when the rise time and fall
time is called 5min a second that time
we find that this area is much larger
that means they say in this particular
the area that will covered by this
triangle will be much higher than when
it is tau is equal to 100 seconds so
this is the current that will flow for
different rise
I mean rise and fall time of the input
signal so this this source how the power
dissipation will change as you change
the rise and fall time and that is the
reason why we insert buffers at regular
interval in a circuit so that the rise
and fall times are not very high I mean
this would be recapped within certain
limit coming to a third important aspect
you can see we have short-circuit power
dissipation for different load
capacitance so initially the load
capacitance is zero and then we have
increased the load capacitance and you
can see the it is the cab is going down
because it will not charge to a higher
level but it did that it will it will
that it will go down and as a
consequence the current that will flow
will be smaller and the area that will
be closed by this rectangle by this
triangle will be less that means when
the load capacitance is increased the
short circuit power dissipation gets
reduced however the the although the
short circuit power dissipation reduces
the delay will increase because of
increased capacitance so from this
discussion what conclusion we can make
so far as the short circuit
participation is concerned there are
then we have seen there are three
important parameters which you can
control one is frequency of operations
but we cannot usually compromise on
performance that's the reason why we
cannot really reduce frequency to reduce
participation however we can reduce Tao
we can also reduce the parameter that is
your sometimes we can reduce the load
capacitance and node capacitance can be
increased to reduce the short circuit
participation and of course the supply
voltage scaling
reduction of the supply voltage is the
most important parameter I mean
important parameter that can be used to
reduce the short circuit participation
so with this we shall we have come to
the end of today's lecture in the next
lecture we shall primarily discuss about
the leakage power dissipation but before
that we shall also discuss about the
dynamic power dissipation due to
glitching there is another power
dissipation that is known as glitching
power dissipation that we shall discuss
in the next lecture
thank you
About this Video
Oct 12, 2025
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