VLSI Circuits & Systems (Tutorial - 3) - Electronics & Communication Engineering Video Lecture - Electronics and Communication Engineering (ECE)

hello and welcome to today's tutorial is
the tutorial 3 this is based on plus
test 2 here are some fill-in-the-blanks
questions first question was in
adiabatic circuits the energy
consumption can be reduced by increasing
- and/or by decreasing - so the answer
is in adiabatic circuits the energy
consumption can be reduced by increasing
T that is the time for charging and or
by decreasing our let me explain to you
how these two are coming as you know in
adiabatic charging you are applying a
variable voltage say V T and through a
resistor and there is a capacitor C and
maybe we will put one switch and this is
grounded at time T is equal to 0 we
assume that the capacitor on this charge
is zero and after that a voltage I mean
time varying voltage is applied and it
is the voltage V and at time T this is
at time T here you have the plot on this
in this you have got time so in time T
it reaches a voltage that says you this
is VC so whenever you charge with the
help of this variable voltage what is
the energy that is being dissipated in
our that can be calculated and this will
be equal to energy dissipated in this
capacitor R will be equal to RC by T
into see VC square so that will be the
equation that we'll get now this can be
rewritten as 2
our C by T into half C VC square now you
know that this is the energy that is
being dissipated in non adiabatic
charging this is adiabatic charging now
with respect to this we find that in
adiabatic charging whenever you are
doing in this way very charging with the
help of a variable voltage which is
which varies over time we find that this
factor is multiplied by 2 RC by T now
when T is equal to 2 RC then this this
becomes 1 and obviously the energy that
is dissipated for charging the capacitor
2 to the voltage VCC will be equal to
half CV square which is same as non
adiabatic charging
however when T is greater than 2 RC that
means you are you charged over a longer
period then what will happen this factor
will be smaller that means this will be
less than 1 and obviously the energy
that is dissipated will be lesser than
the non adiabatic charging so I you can
you can one way of reducing the power
dissipation energy consumption can be
reduced by increasing T another
possibility is that you can reduce the
value of R so keeping T reducing the
value of R also you can reduce the
energy dissipated in the in adiabatic
charging so that is the reason why here
is the answer in adiabatic circuits the
energy consumption can be reduced by
increasing T and or by decreasing our as
I mentioned by increasing T the power
dissipation decreases because the
the voltage across this resistor reduces
whenever you charge it slowly that means
the energy dissipated across this
resistor is is reduced so if it is it
can asymptotically increase it can
become zero whenever RT is very large so
T is that is infinity then obviously the
power dissipation will be small but
however in real life what you can do you
can make T as long as possible and as a
consequence the voltage difference
voltage that is applied across the
resistor R decreases that means the
charge whenever you you keep on charging
the voltage here that is being built up
because of charge accumulation in C will
be very close to VC T and then as a
consequence voltage difference will be
Delta V and that will be smaller and
smaller as you increase T so that is the
reason why by increasing T you can
reduce power dissipation now the second
question was older process technologies
have - constant and present the
technologies have that - constant
leading to larger dose - loss so the
answer is older process technologies
have one sided constant and presently
technologies have two-sided constraint
leading to larger yield loss you may
recall that because of process parameter
variation the channel length varies in
this manner so this is the typical L and
say typical and around it it changes its
its a random variable and as you mean
Gaussian distribution you can see the
the channel length is varying of a
certain range it is it cannot be
considered as a constant now as you know
in all older technologies say less than
180
howdy cancer get up them sorry get up
there 180 micron technology what was
what was happening in whenever sorry
poor 0.18 micron technology 180
nanometer technology so whenever the
technology was greater than 180
nanometer then what was the situation
the leakage power was insignificant
compared to dynamic power
so when leakage power is insignificant
compared to dynamic power dynamic power
as you know is proportional to CL PD d
square F now in this whenever you change
the channel length when the channel
length varies over a range this
parameter CL changes because whenever
the channel length is longer obviously
the capacitance will be more because CL
is proportional to L into W so as the
length increases the capacitance
increases and al as L decreases
capacitance decreases so the the one
sided constant was like this that means
the the dynamic power dissipation was
increasing like this this was the
dynamic power and similarly delay was
also increasing with the channel length
so we can see here the because of this
the both channel length I mean both the
in on this way in this direction you
will have delay and power so delay
increases because of the increase in
capacitance so this is your delay and
this was power now if your pause by
budget is exceeded here and delay Bizet
that means performance is exceeded here
then this is the yield window
this is the ield window that you will
get that means the devices which are
falling in this range that means fortune
having channel length in this range have
to be discarded so this is the one sided
constraint in older technologies however
in pressure in the present day
technology is say in 70 nanometer or say
maybe 45 nanometer as you know the the
static power a static power dissipation
is greater than dynamic power that means
not only static power is significant but
is the some it is more than the dynamic
power as you know in 70 nanometer it is
about 52 percent of the total power that
means static power dissipation is larger
so in such a case what will happen as
the channel length you know decreases
what happens the thinner because of Vth
roll-off the threshold voltage decreases
that means with the decreasing channel
length the threshold voltage decreases
and as the threshold voltage decreases
the leakage current increases
exponentially as you know that sub
threshold leakage current is dependent
on the threshold voltage and as a
consequence the equate the power is now
like this so in new technologies there
is the you can say this is old this is
also old technologies and this is the
new technology so in this case what is
happening because of power budget you
can say for delay budget let's assume
this is the window I mean you have to
discard these because they are not
satisfying the performance but because
of power because of heavy leakage let's
assume this is the maximum leakage power
dissipation or total power dissipation
that you can tolerate so we find that in
this direction here you have to discard
additional devices and our additional
devices have dies because of the
increased power dissipation so now you
have got to say
Podcast two-sided constants so in older
technologies it is one-sided constant in
new technologies we find that in the
present day technologies it is a
two-sided constant and because of this
constant two-sided constant what is
happening more dyes are to be discarded
leading to a loss so that's why here old
process technologies have one-sided
constant and present day technologies
have two-sided constant leading to
larger a loss so that was the second
question coming to the third question
adaptive body biasing is a - technique
that allows tuning of each dye to
achieve - so answer is adaptive biasing
is a post silicon technique that allows
tuning of each dye to achieve higher
yield so as we know we have discussed
several techniques of reducing power
dissipation I mean to achieve to achieve
higher yield
that means adaptive body biasing is a
technique that allows tuning of each
each adaptive body biasing is for
silicon technique we have discussed you
know we discussed in our lecture on very
variation tolerant design we discussed
some techniques which are for silicon
and some techniques which are pre
silicon so pre silicon techniques are
essentially designing suitable using
suitable technique so that the variation
is tolerated so you will do the design
in such a way that it will be variation
tolerant on the other hand in for
silicon techniques after the fabrication
you will do some adjustment that can be
done by using by applying different
supply voltage or by applying different
body bias so different dyes will be
applied different body bias so the
answer is adaptive body biasing is a
post silicon technique and that allows
tuning of each dye to achieve higher
rated
okay so that was the third question
fourth question was - is a standby
leakage reduction technique and this is
a runtime leakage reduction technique so
I have discussed many several standby
leakage reduction techniques you may
write any one of them here so either
variable threshold voltage CMOS vtcmos
where you can change the threshold
voltage by changing the body bias or MP
CMOS where you can do power gating when
in standby condition or you can do
transistor stacking that means so far as
the standby leakage reduction techniques
are concerned standby leakage reduction
technique
there are several techniques one is
transistor stacking or which is self
biasing as you know if you apply
different input input combination to a
combinational circuit when the
transistors are in series because of
cell bias for a particular input voltage
there is reduction in leakage power that
is the transistor stacking so you can it
could have you can write in stir
stacking or VT CMOS variable threshold
voltage CMOS in which the threshold
voltage is varies by changing the body
bias and third technique that was
discussed is mtcmos multi threshold
voltage CMOS where you can use multiple
threshold voltage in series you may
recall so this is the actual circuit and
you can put transistor either in the as
header or footer to reduce the leakage
current so this is also known as power
gating so you can use any one of the
three tagging right you wanna in any one
of the three techniques here VT CMOS
mtcmos or transistor stacking and
similarly for runtime leakage reduction
technique the most common approach is DT
CMOS where dwell threshold voltage CMOS
is used
that means transistors some transistors
are which are on the the gates which are
on the critical path those gates are
realized with lower threshold voltage
and gates which are on the non-critical
path they are realized by using high
threshold voltage so duty CMOS is one of
the runtime leakage reduction techniques
and so this is this is the answer you
can give then question five was voltage
scaling reduces leakage power
dissipation because of deaths and death
humanik you may remember that voltage
scaling is commonly used for dynamic
part
reproducing the dynamic power because
you know that dynamic power is it's
proportional to VDD square but you can
say there is a side effect side effect
is that if you reduce VDD by several
techniques it can be static voltage
scaling or it can be dynamic voltage
scaling whatever you do as you reduce
the supply voltage the leakage power
reduces because of two factors one is
your deep and drain induce failure
lowering so when the drain voltage is
reduced the barrier is lowered barrier
lowering occurs and as a consequence the
as this as the supply voltage is reduced
so for the the barrier is higher and as
a consequence you know the leakage
current is lesser that this threshold
voltage is larger similarly G idividual
effect that is your grating gate induced
drain leakage that also reduces affects
the voltage scaling and for larger
voltage the leakage current due to G
ideal effect is more and for smaller
voltage is this so because of these two
effects you know as you do voltage
scaling there is leakage power reduction
then coming to a sixth question signal
isolation is used in power gating
circuit to overcome - the answer is
signal isolation is used in power gating
circuits to overcome short-circuit power
you may recall that so whenever you are
using say multiple voltage domain in a
circuits let us assume this is a power
gated block so this is there this is a
power boated
power gated block so since the his power
gated block the output voltage that is B
that is generated here it can be either
0 or VDD but I'm thought for example if
you use say header switch then the then
the voltage will be as you turn it off
voltage should come down to 0 but it may
not come down to 0 because of various
reasons because of the leakage power of
this part because of a little catch
power of this part even when it is
switched off there is some leakage
current that will flow through it
as a result there will be a voltage and
that will be generated here so if this
output goes to a non power gated block
so this is non power gated then what
happens if this voltage is greater then
V V TN is greater than VT N and less
than VT P sorry VDD minus VTP then what
happens if it is get up then this that
means V in that V out you can say here V
out is greater than VT n but less than
VDD minus VTP
then what will happen in this part of
the circuit there will be short circuit
power as you know in an example in case
of an inverter if the voltage is input
voltage is greater than VT n this
transistor is on and if the voltage is
less than 50 D minus VT P this
transistor is also on as a result both
the transistors will be on leading to
short-circuit power
or crowbar power so this this this this
is the situation and that is the reason
why this this output is isolated with
the help of suitable hardware so we will
put an put an in my and gate here this
output will be fed sorry we will put an
N get here this this will go there and
this will come here and isolation signal
signal will be applied here so that
whenever this is isolated this will be
this will be clamped to low level so
that it does not disturb this part of
the circuit that means this is low this
will be low so these are this gate of
course has to be it should get always
this should default this and this end
gate should not have should not be power
gated so this is how it can be done so
signal isolation is used in power gating
circuit to overcome short-circuit power
so signal isolation can be done with the
help of and gate or gate or some other
hardware as I have already discussed in
detail coming to question 7 mtcmos based
power gating used to minimize - leakage
power so as you know empty CMOS Western
I have already discussed mtcmos based
power gating is used to minimize standby
leakage power mtcmos based power gating
is essentially is essentially you are
putting high 50 10 stirs in series so
you will be applying slip control signal
here and that will and when the circuit
is in standby then these transistors are
off and as a consequence leakage power
will be less so you can say this empty
CMOS is used to reduce
standby leakage power so mtcmos based
power gating is used to minimize a
standby leakage power
okay so coming to question number eight
in dwell VT circuits the - transistors
are used for DES and low VT transistors
are used for DES so whenever I have
already discussed about DT CMOS as you
know in well VD circuits high VT
transistors are used for leakage power
that means in a multi-level multi-input
circuit you have got many gates cell and
a larger portion of them are in are in
non-critical path so the gates which are
on the non-critical path you can use you
can use in high threshold voltage
transistor to realize them so that will
reduce the leakage power so high VT
transistors are used to reroute leakage
power on the other hand the gates on the
critical path they are to be realized by
using low fifty ten steps so that
performance is maintained so you can say
hi every transistors are used for
leakage power or rather to lead reduce
leakage power and low VT transistors are
used for performance higher performance
so lower linkage power and higher
performance you can see Oh coming to
question number nine multi ferritin
stirs can be fabricated using - and -
techniques so I have discussed several
techniques by which you can realize
multi VT circuits that means the
transistors with multiple threshold
voltages so the the various techniques
are number one is multiple oxide
thickness
it can be multiple channel lengths you
can use multiple body bias
so there are these are some of the
techniques that I mentioned and also you
can do multiple channel doping so I have
discussed how these techniques can be
used and how the threshold voltage
varies as you realize transistors with
different silicon dioxide thickness that
means the width of the silicon dioxide
layer in the in realizing transistor
similarly multiple channel length I have
already mentioned that smaller the
channel length larger is the threshold
voltage smaller is the threshold voltage
but that means because of ETH roll-off
so as the as the channel and reduces
threshold voltage decreases so multiple
channel and can be used to realize
multi-threshold voltage no multiple
threshold voltage similarly multiple
body bias can be used to realize
transistors of different threshold
voltages similarly multiple channel
doping so you can rise right any one of
the two any two of the four so multiple
t ox that means multiple silicon dioxide
thickness or multiple channel length i
have channel doping I have written but
you can write any two of the four
techniques that I mentioned then nine
question number ten is leakage reduction
in transistor stacking occurs because of
Dash and dash mechanisms you may recall
that whenever you do transistor stacking
like this say several transistors are in
series
say and depending on which of these are
on and off the leakage current varies as
is for example you have applied zero
zero zero zero voltage zero level
voltage and now some leakage current
will flow and as a result some voltages
maybe say 0.18 here and maybe point
three six volt here and some some other
voltage here maybe six point six four
volt here so as you can see some
positive voltages are developed as these
source points and this leads to
reduction in leakage current because of
three mechanisms number one is as you
know since the source voltage is
positive and gate voltage is negative
you know gate is reverse biased and as
you know whenever you reverse bias gate
with respect to source this reduces
sub-threshold leakage currents so
reduced subsys old leakage current
second is the voltage across this
transistor is small as a result you know
because of that DIBL effect because of
smaller voltage across the transistors
and weak a smaller drain voltage that
the ivl component of leakage current
will be smaller whenever you do this
transistor is stacking and third reason
for reduction is because of reverse body
biasing so reverse body biasing is will
will lead to smaller threshold voltage I
mean larger threshold voltages and as a
consequence the the leakage current will
be smaller so you can write any one of
the three so I have written reverse body
bias and div L so any one of the three
techniques it also reduces sub threshold
leakage current so you can write any two
of any two from the three mechanisms
that is responsible for leakage current
reduction in 10 star stacking okay
coming to eleven maximum switching
activity for directors for in two's
complement from thorne occurs when this
is smaller and data - you may recall
that there are two parameters dynamic
range and correlation factor these two
parameters are responsible for you know
reduction in reduction in dynamic power
so that because of reduction in
switching activity so when the dynamic
range is small as you know because of
you know in two's complement form
what happens that sign extension occurs
because of sign extension you know as
the it is suppose the changes from plus
0.3 volt to minus 0.3 volt and dynamic
ranges say 15 volt then what will happen
the most of the most significant bits in
this case in for positive these are 0
and for negative it is will be 1 and as
a consequence the there will be lot of
switching activity so when the dynamic
range is small and the sign changes in
two's complement form that leads to
larger switching activity
similarly the correlation factor because
of correlation factor the switching
activity changes for example if the
input changes slowly increases or
decreases then the in the consecutive
data are anticorrelated as sorry
correlated as a consequence the
switching activity will be less on the
other hand if the if it changes say from
negative it goes become positive then it
becomes negative and again it becomes
positive so it is highly anti-correlated
so in this in this case again lot of
changes will occur or if you can save
the changes very quickly then data is
anti-correlated so in these two
situations that means when the dynamic
range is small and data is
anticorrelated the switching activity
maximum switching activity occurs using
two's complement form and as I mentioned
this can be reduced by using
sign-magnitude representation of data
when you send it over some bus
question number 12 was module level
clock gating I didn't is identified by
desk whereas the install 'evil clock
gating is commonly identified by this
you may recall that this whenever you
are using power gating you can either
use some automated CAD tool but the
whenever the module level clock gating
is done I mean here it is clock gating
not targeting Bickler the clock gating
is done in module level say l you then
say transmitter-receiver when they will
be off these are usually identified by
the user
that means module level clock gating is
identified by the user or the designer
on the other hand when the clock gating
is automated clock gating tools are used
massively clock gating techniques are
available nowadays where CAD tool does
the clock gating automatic insertion of
clock gating hardware in the circuit so
in such a case the CAD tool does the
necessary clock gating that is the
reason why the answer is module level
clock gating is identified by the
designer
whereas register level clock gating is
commonly identified by CAD tool so
coming to question number 13 boss in vs.
coding is dash and dash encoding
technique you may recall that there are
several ways by which the coding
techniques can be in categorized one is
your one category is redundant
another is non-redundant then whenever
you are using redundant encoding there
are two alternatives one is your
one-to-many static or it can be one too
many dynamic so these are encoding
techniques
redundant means the whenever you are
sending here is your encoder
and here is your decoder so to the
encoder say n bits are applied and it
generates M bits when M is greater than
n then it is redundant and as you know
when M is equal to n then it is non
redundant so when more number of
additional bits are used it is redundant
technique and there you can have two
possibilities in the first case you know
you have got encoder and decoder encoder
with memory encoder with memory and
decoder memory less this is a situation
one-to-many static that means in the
encoder will be using memory and decoder
will not require any memory and that is
the situation in bus inverse and
encoding so it is a redundant and
one-to-many
static encoding technique on the other
hand you may require both I mean encoder
and decoder may have memory that means
both will be with memory so sorry this
is the encoder with memory and decoder
also with memory in such a case we call
it one-to-many dynamic that means when
encoder with memory and decoder with
memory it is one to many and as you know
I discussed t0 encoding in t0 encoding
you may recall that memory is required
in implementing the encoder as well as
the decoder so it is a one-to-many
dynamic technique but so far as this
particular technique is concerned bas
inverse encoding is concerned it is a
redundant and one-to-many static
encoding technique so coming to question
number 4 it is necessary to introduce -
when a signal is sent from a low voltage
domain to high voltage domain circuit so
it is necessary to introduce
introduce level converter when a signal
is sent from low voltage domain to high
voltage domain circuit so rhythm is same
as reason is same as you know whenever a
signal is passing I discussed about
techniques where you know you have got
say two voltage domains so this is your
low voltage domain say maybe say one
point two and it is going to another
voltage domain and here let's assume the
voltage is two point zero so whenever a
signal low voltage domain signal goes
from low voltage domain to high voltage
domain what happens this voltage will be
there is a possibility that output level
voltage will be in this range it will be
less than that means V out will be get
up than VTN and less than VDD minus TP
and that will lead to you know
short-circuit power dissipation in this
part of the circuit so to avoid that
we'll be introducing level converter LC
and that will be fed back instead of
directly applying so you will be using
level converter which will raise the
level to a high level there's the low
level to high level as the signal goes
from low voltage domain to high voltage
domain so the answer is you have to
introduce level converter when a signal
is sent from a low voltage domain to
high voltage domain circuit question
number 15 is a feature size of a MOSFET
device is reduced by a factor s the
device
delay and power of the scale device
become - and does respectively as there
is a feature size of a MOSFET device is
reduced by factor s the deal the device
delay and part of the scaled device
becomes 1 by yes you know this this
occurs because you know you are reducing
both three parameters you are reducing
one is length second is width and third
is silicon dioxide thickness and as you
increase the width and
that capacitance CG is proportional to
is dependent and on three parameters W L
and C sorry that do X and actually t o X
will influence in different way and then
W and L so as you increase W and L I
mean reduce WL it will be W by s and it
will be L by s on the other hand as you
reduce the silicon dioxide thickness
what happens the capacitance increases
so here the parameter will be multiplied
by s so effectively gate capacitance
will be CG - will be equal to CG by s
and as a consequence the delay will
reduce by Factor s and and the sephorus
power dissipation is concerned it will
be proportional to 1 by s squared
because you know the the because of the
reduction in voltage the and that will
also reduce in it will also reduce the
drain current because of reduction in
voltage as well as reduction in trend
current the power dissipation PD
power dissipation is proposed is equal
to P by s square reduces by a factor of
H square so I have discussed it in
detail coming to question number 16 code
morphing software used in Crusoe
processor is - essentially it is a
dynamic code translation software as you
know that code code morphing software
translates from one one instruction you
know one type of instruction of a
processor to another type of instruction
set so
from say that you are using for example
your Pentium processors which are
essentially realized by using
superscalar technique on the other hand
that be liw technique is used in
realizing crusoe processor so 1
instruction set instruction you know
architecture to another instruction
architecture it does the translation and
that's why it is called dynamic code
translation software essentially
translates code from one type of
processor to another type of processor
so it is a dynamic code translation
software coming to question number 17
realize a fully adiabatic to input and
or gate I discussed about the steps that
you have to follow in realizing in
converting a non adiabatic gate to
adiabatic gate first thing to be done
replace each of the P Mo's and n MOS
devices in the full up and pulldown
network with T gates
ii is used expanded pull-up network
could drive the true output and use
expand a pulldown network to drive the
complementary output third is both
networks of the transformed circuit are
used to charge and discharge the load
capacitance and 40s replace VDC VDD by a
pulsed power supply with varying voltage
to allow adiabatic operation so let us
consider two input or nor gate so in a
non adiabatic invert an two input nor
gate is realized in this way so you will
require two
so this is a this is nine so this is not
nine so it will be this is the nor gate
two input nor gate that is realized by
using non adiabatic technique so you
have to convert it say here you apply a
and B and you can write a and B so this
is the nor gate that you can realize by
non-native editing you have to convert
it into adiabatic circuit so you have to
replace each of these transistors by a
transmission gate so what you will do
say let us consider this part so here
you have got two p MOS transistors in
series so you will put two transmission
gates in series
and this will drive a capacitance and
what will be the inputs so here you have
applied a and B so you will be a and B
and here will be B bar and a bar and
here you will get nor output naught that
means a or B bar now then we will
realize this part so we have considered
the this part and now we shall consider
the full down network so full down
network 2 are in parallel so you will
require 2 transmission gates in parallel
new transmission gets in parallel and
that will drive the output capacitance
so here you will get or and what will be
the inputs the a and B will be here
applied here a and B air will be a bar
and B bar so and finally here and the
last step is you will be applying false
power supply that means you have to
apply pass pause for roughly so you are
realizing or that means a plus B and
this is realizing nor a plus B bar so
this is how you can convert any gate
CMOS gate to a fully adiabatic yet this
is fully adiabatic gate because it it
does fully adiabatic charging and
discharging with the help of this pulsed
power supply so we will have dwell
output nor and or and how it can be
realized I have explained so this is the
realization coming to question number 18
find out the switching activity of a
module module o7 counter using binary
and gray codes for static encoding so
this is the binary code is the binary
code and this is the gray code so you
can see here in a mode in a counter the
transition occurs I mean it will go from
say s 0 to s 1 then and in this way it
will go to s 7 and again it will come
back to s 0 so this is how the counter
occurs
I mean operates so you can it will be
various states are if we use binary
coding s 0 is 0 0 0 s 1 is 0 0 1 then 0
1 0 and so on so you have got seven
states because up seven corpse and
whenever it goes from 0 0 0 to 0 0 1 so
transition is 1 whenever it goes from 0
0 1 2 0 1 0 transition is 2 because 2
bits are changing
and from 0 1 0 2 0 1 1 and 1 bit
changing and from 0 1 1 2 1 0 0 3 we
changing and from 1 0 0 to 1 0 1 1 bit
changing and from 1 0 1 to 1 1 0 2 bit
changing and whenever it goes from 1 0 1
1 0 to 0 0 0 2 bit changing
so number of transitions is 12 on the
other hand if you do gray coding the
codes are 0 0 1 0 0 0 0 0 0 0 1 0 1 1
then 0 1 0 then 1 1 0 1 1 1 and 1 0 1
and you can see for these 6 from these 6
transitions the only one bit will change
0 0 0 2 0 0 1 1 bit 0 0 1 2 0 1 1
another big change and from 1 0 1 1 2 0
1 1 1 bit change so there will be 6 1
bit changes will occur however whenever
it goes from state 7 to state 1 so 1 1 0
1 2 0 0 0 there will be 2 bit changes so
total number of transitions is 8 so you
can see how the switching activity
changes in modulo 7 counter for the two
cases binary code and gray code ok then
the question was 99 question number 19
was proved that the charging of a
capacitor C in n steps to a voltage VDD
instead of a conventional single step
charging reduces the power dissipation
by a factor of n so whenever the
charging is done in one step as you know
the part is energy that is dissipated is
CL this v square by 2 where V is the
voltage and as you do n step charging
and obviously in each step the voltage
charges from any further in the first
step from 0 to V by n in the second step
everybody in - I mean stepwise it will
keep on doing so you can see here energy
dissipation in each step of charging
will be CL v square by 2 n square
because the voltage here is V by n so CL
by 2 into V by n square so that gives
you CL v square by 2 n square so this is
this is for each step of charging now it
will require n steps are charging so the
N into each step that will be equal to
CL v square by 2 n and if you compare
with the first case 1 that means the
first situation one-step charging is
step by e is equal to 1 by n okay okay
let now let me consider some other
questions
so there are several questions you have
given so
so one of the questions were idea of
attic logic circuits operations I have
already discussed that adiabatic logic
circuit and another question was the
normalized delay sizing how the delay
changes with sizing factor so let me
answer the questions which can be
discussed in this short time one
question was as you this is the sizing
factor and is the normalized delay
what do you really mean by sizing sizing
means you are increasingly you are
increasing the size of the transistors
how you are increasing the size
obviously by increasing W by increasing
W we are increasing the size of the
transistors and how the delay changes as
you increase the fan-out that means that
there is a relationship between fan-out
and sizing factor so when the fan-out is
small so when the fan-out is small the
delay with sizing factor changes this
way that means initially as you increase
the size the delay reduces but after
some time delay it does not you know as
you increase defense fan-out delay
increases the reason for that is as you
increase the size you know there are two
things you are driving and say inverter
of a larger size now if this capacitance
is large if this capacitance is large
the the capacitance delay will reduce if
you increase the size of this transistor
but you know that as you increase the
size of this transistor the capacitance
of this also increases and as the
capacitance of this increases there will
be larger delay for this side that means
that is the reason why for a given
capacitance if there is an optimal value
of size and beyond that it will increase
because it driving and the capacitance
is increasing of this that will lead to
larger delay here so there is an optimal
size for which it will get minimum delay
and beyond that as you mean if if you
increasing sizing factor then delay will
increase now that will be dependent on
the fan out fan out means deferring a
different value of capacitance if the
capacitance is small then the the effect
of sizing is
that means reduction is delay is smaller
when the capacitance is small and
reduction in delay will be larger
whenever this capacitance is larger so
when this that means here fan-out is 6
and here safe an out is equal to 3 that
means when the fan-out is smaller that
means this capacitance is smaller fan
out means you know it is driving lesson
number of gates when the fan-out is
equal to 3 and whenever you are driving
more number of gates then fan-out is
more so capacitance is more when the
fan-out is more and that sizing will
have more impact on delay when the
fan-out is more and when the fan-out is
less it has lesser impact however again
there is an optimal sizing factor beyond
which delay will increase in both the
cases so that is what I explained so I
believe the other questions we can take
up in the normal class and we can
discuss in detail with this let us
conclude this tutorial 3 and you can
take up other questions in our normal
class thank you
you