CPU - Memory Interaction - Computer Science and Engineering Video Lecture - Computer Science Engineering (CSE)

ha ha ha ha they just need a buddy
I was Columbia shall I
teach
so the previous lecture we saw how
memory generally gets organized and also
saw some details about the memory
different classes of memory not really I
would say in a very systematic way okay
if we saw a few things which are
important for general understanding and
from practical point of view good now
we're talking about it we said that
essentially it is the speed match
between the CPU and the memory module
which gives rise to this hierarchy of
memory let us we talk about the type of
memory which can interact with the CPU
at the CPUs speed itself the one that is
slower and the one that is further
slowest okay so we are talking about
that now before we go into the details
of the memory there are a few more
points we have to take note of what is
that first is we always talk about say
something like an 8-bit CPU 16-bit CPU
and so on or 32-bit CPU okay now how the
memory is organized with reference to
these different types of CPU right does
it mean that if you have an 8-bit CPU
the memory must also always deal with
8-bit data because essentially when we
talk about an 8-bit CPU what exactly we
mean is internally the CPU process can
process 8-bit at a time that is what the
word size okay then if it if it is
16-bit CPU essentially what we mean is
internally the CPU is capable of stream
bit processing that is processing 16-bit
data as one unit now that may be so for
instance you may be having a 16-bit CPU
but the memory
not really have a word of 16-bit void
can still have okay the unit that is the
word we call it loosely that may be
still an 8-bit sighs okay 8-bit size
word that is a byte so generally what we
say is the memory is usually byte
organized now there is a specific reason
for that okay now when we say the memory
is byte organized which deals with CPU
which is 16-bit okay clusters classified
as 16-bit CPU then essentially a byte
which is one 8-bit two unit so to such
bytes must be brought in here okay we
are not really talking about what is the
bus with here it is meaningful if the
bus is also a 16-bit way so that in one
go the CPU may fetch the entire unit out
information it can process and then
carry out the processing but then the
memory may be byte organized by that
what I mean is whenever the CPU needs it
can always go and fetch less than 16-bit
data also okay see that is what you
memory organization permits that is what
we mean okay in other words we can talk
about a low byte and a high byte
together forms one 16-bit board okay now
anytime this low bank can be separately
addressed and then brought high weight
can be separately of address and there
brought if necessary that is what we
mean so we have this what we may call as
the data size of the CPU and the way we
organized on the memory side which
generally we keep it as byte organized
now because of this we have different
class of CPU itself what is that
suppose we will continue with this
example of 16-bit CPU okay as indicated
here it essentially consists of 16-bit
word and it has consists of the low byte
and a high bit this what we have from
the cpu L now Ida memory in right
suppose let us just take a look at this
that it is a byte organized memory which
means the width of the unit of
information that is addressable okay is
byte wide then we can talk about this as
location 0 location 1 location 2 and so
on fine now there are two types of
processors for instance suppose this
location 0 holds the low byte and
location 1 holds the high byte let's
together these two bytes are needed for
the processor okay now location 0 has
the low byte location one has a high bit
now this our particular one is called
yet as you can see the low order byte
comes first in the in this location this
is a first location now so the low byte
the particular thing comes in the first
so this arrangement is called a low of
low order byte first right low order
byte first this call and it is also
known as little endian arrangement
meaning the processor is generally
called a little endian processor the one
okay where is to base may come from the
memory then whatever comes from the low
the first location that is location zero
will be the low order the other one
right will be the high order so then
such CPU will be called a little Indian
CPU now it can be the other way also now
instead of this you can also have an
arrangement like this in which location
zero right occasion zero may hold the
high byte and location one may hold the
low byte okay together still we have the
16-bit data so what we are talking about
here is the memory organization mainly
because it is a byte organized memory
and the processor is 16-bit processor is
capable of dealing with 16-bit data now
this particular one this one obviously
will be called what the high order of
the byte comes in the first location so
that will be called high order byte
first so I'll just write the
simplification the abbreviation of it
instead of low order byte first what we
have this arrangement is a high order
byte first and as you can see this other
one is called a big-endian cpu okay like
this one is a little endian cpu here
this one will be called a big-endian cpu
okay now body types of CPUs are in use
for instance I would like you to take a
look at how Intel CPU organizes its data
and how mortal or Graces is down 16-bit
data and then see which is little-endian
and which is big-endian okay you may see
that for yourself good now from the
memory point of view as long as it is a
byte organized memory what we say is
it's going to hold one unit of byte
which is addressable right from memory
point of view this rather is low or high
does not matter because it is the CPU it
is going to fetch this data and then
proceed on the other hand instead of
16-bit CPU if you have an 8-bit CPU
right so here also the unit information
is going to be just one bite right okay
fine
now this is one point now another thing
is this is as far as the data part of it
is concerned now let us just take a look
at the address part of the CPU also that
is the CPU places the address and how
this address may be used in say
addressing the memory or choosing
different parts of the memory and so on
okay we know that if we time n bit
address what will be that the total
address space will be 2 to the power M
okay that is we talk about the total
address space is also sometimes called
just the memory map okay
the map of the memory the total address
space this whole thing would be of size
2 to power n that is because of the N
bit address okay now let us draw a a few
sketches and then try to see how we may
make use of this n bit address in say
addressing the memory okay so let us say
I think I will assume for simplicity
sake for sake of simplicity that the
address size is a bit okay it's okay the
same logic you can extend for 16-bit
also that is we have address let us say
from a knot to e7 okay that is it is an
8-bit address I am assuming a knot to a7
so with this what is it tooth for 8 the
maximum addressability is only to 256
okay - Tori 8 ok that does not matter
now let us see that I can go to maximum
of 256 locations okay that is what I can
have only memory side now supposing I
take this bit a 7 specifically okay bit
a 7 and then use it as one of the inputs
to the memory part
kay this can be an address input to the
memory this is just some memory can be
one address input or it can also be one
of the control inputs we are not really
seen
I will possibly introduce okay now I
will just call this something like an
enable signal which when on the memory
chip power system whatever it is is
activated okay for some work right if it
is at the chip level then generally we
call it as a chip enable input now this
particular one only enables this memory
chip
I am so for effective address I get one
bit less note right it only enables
means this block is enabled now on the
other hand just see what I am doing I
will take the same thing same bit input
and then let us say I invert that and
generate another signal it will call us
a seven bar and then have another memory
say chip okay which I give to the other
its chip enable input that is the chip
enable input this is a cheap energy now
what does this mean
whenever a seven is zero this will not
be enabled so this part of the memory
will not be in use whenever a seven is
okay when it is 0 this is inverted and
this will become one so this is enable
and whenever a 7 is 1 this is enable
whereas this is not enable so at any
time depending on whether a 7 is 0 or 1
either this or this appropriately is
enable now the rest of them okay a not
to a six so I can give it as an input
okay
this rest of them that is a not to a six
which of course are derived from here
okay though not shown specifically the
same enought t6 I may give to this also
a not to a six
okay so that of course is the address
input
fine now when the memory chip is
addressed of course the other kind of
signals like readwrite all those things
also must be given not showing them here
when it is enabled and then say
appropriate control signal like read
comes it will produce the data no fine
that data will be going to the data part
of the bus and it will go back to the
CPU okay all right that will just mark
it if necessary we will discuss or we
leave it so the address input to the
memory comes from the CPU and also the
necessary control signals read or write
similarly the data output from the
memory that one will be going to the CPU
okay maybe I will just show it here okay
so this is the data part which goes to
the CPU if H by - it may come to this
and also go there now let's not worry
about the data partial image and I also
said the control signals are needed so
let us not worry about that for our
discussion now now what is it I have
done as long as a seven is one this chip
will be enable and as long as a seven is
zero this chip will be enable in other
words okay now here therefore the total
address space here every n yeah we have
8 bit right so 2 to the power a 256 we
have and a 7 is the most significant bit
fine
so for the most significant bit when it
is 0 means it is the lower part of the
address space when the most engine bit
is 1 it is the higher part of the
address space that is if this is the
lower part this is location
zero okay Louis part and this one
corresponds to the highest location R to
the power n minus one okay in our case
it will be four eight it will be two to
the rate is 256 and so this is location
number two five five because we start
from zero we go up to 256 so from zero
to one location one two seven that is
lower one okay this is location zero
same and location 0 to 1 to 7
corresponds to a seven being zero right
so this will correspond to a 7 be zero
and this part will cusp onto a 7 being
one five so now this total address space
we are making use of in this particular
manner okay
this argument you can extend to any n
bit fine so you can see that apart from
the address input to the memory chips
the same address output from the CPU can
also be used not only as input to the
memory but also for specifying some
control signals in this case we are
using for enabling the part and so you
can say that this location 0 to 127 is
going to be accommodated in this memory
chip and location 1 to 8 that is the
next one right location 1 to 8 to 255
that one is going to be accommodated
here fine now let me
all right alternately just extend this
logic little further on the other hand
instead of using a seven I'm just
extending the instead of a 7 and a not
as shown here okay if I take two memory
blocks or two memory chips as before
okay instead of a seven just see if I
use a not here use it for chip enable
and invert
and use that this is a not right and
this is a not bar inverter this I use it
for chip in a bro and if I use a not I
have you so a 1 2 is 7 now see for
yourself what is the difference between
these 2
we saw that a seven being zero it is the
lower thought a seven being one it is
the higher part of the total address
space now in this one this is the
address bus just like what we had here
now we have two different schemes here
in this the LSB is used okay we can say
but of these sad rest bits the MSB or
most enduring bit is used for enabling
here the least significant bit a not is
being used for enabling what is the
difference between these two okay
when when we set now the same argument
we said whenever a 7 is 1 this will be
enable whenever a 7 is 0 this is enable
same thing holds good here also whenever
a naught is 1 this will be enabled
whenever a naught is 0 this will be
enabled right when is it just take even
3 bit address assuming or a 4-bit
address let us say let us just do four
or 4-bit address
okay when do you find this is your a
naught this is your a 1 this is your EA
- this is your III this in other words
this one is the most significant bit
this is the least significant bit in the
case of this s7 will be a must be that
does not matter okay now just see what
is happening what is the next number
next will be 1
the other number will be I mean the next
number will be 1 0 then you have 1 then
like this what is the pattern do you see
here
you keep saying for every alternate code
there is a dress code
this LSB keeps becoming alternately 0 or
1 right now what is the equivalent value
in decimal of this this is 0 in decimal
this will be 1 this will be 2 this will
be 3 this is 4 this is 5 and so on so
whenever we say whenever ultimate thing
you find that these locations addresses
correspond to even addresses that this
correspond to all addresses in other
words right this particular one memory
block tower memory ok block or group
will be corresponding to a not being 1
which means odd so this is all odd
locations will be here all even
locations will be here
fine you see it useful in some way yes
in some places is useful find for
instance here see if you just see all
even bytes will be low bits all orbits
will be high bytes is it not so we can
possibly store our bytes this even bits
here and then make this of this scheme
and then address these bytes
appropriately this is also useful okay
so in other words here what you can see
is location 0 comes from this block
location 1 comes from this block the
other way location 0 comes from this
block location 1 comes from this block
the contents I have to say the contents
of location 0 come from here the
contents of locations 1 comes from here
contents of location 2 like that so in
other words is like ok alternating
interview ok interleave so this in fact
is called an interleaved memory
organization ok now all these comes just
because of the way you're choosing the
address and addressing the memory pod is
so this is an interleaved memory
organization and this particular one you
are talking about blocks contiguous
addresses here right contiguous
addresses location 0 1 2 3 4 up to 127
so you talk about a block so this kind
of starting from MSB actually live leads
to the design of memory by blocking them
so we generally call each of these as
blocks of memory okay so you can call
this as C SM must be 0 for enabling the
so this is the low block and this is the
high block of memory why now instead of
a 7 if you choose some other say a 6 let
us see okay then it will be another
block okay the same way for instances of
a not if you choose a one fine just say
a one is right here you can see that
these two 0 these two one
these two zero and so on so then your
interleaving memory taking two locations
so like this can go on doing fine so
that is about this interlude memory part
of it one thing I would like to indicate
here yes you see this a naught to a 6
that is we have taken seven bits and
then the 7 bit code will have to be
decoded oh yeah
7 bit correct a not a 607 bit and so to
torsion 128 so that will have to be
decoded here okay whereas here we take a
7 and directly give us 1 now next we
will do one more thing we will take a 7
and a 6 right just for example a 7 & a 6
and then see what we will be getting out
of that
instead of taking only a seven if you
take I mean that's a seven for chip
enable if you take a seven and a six
for instance we will get like this that
is a seven is used for enabling this
part of the memory this block of the
memory and a six for the other block now
because a seven a six both are being
used for the chip enable right now
obvious that when a seven is 1 this will
be selected when a 6 is 1 this will be
selected
of course when both of them are 1 both
will be selected so let us not worry
about that now
so because we are using a 7 & a 6 we are
left with only a not to a 5 and that is
what is being used to address this space
these two specific blocks okay
so thereby we are our addressing rage
comes down addressing capacity comes
down so let us not worry about that what
I am interested in showing you is in a
not FA use like this we can decode the
entire N or TFA it is a 16-bit and get
one off to the power 6 it a not efi
there are six bits and so the addressing
address space size will be 2 to the
power 6 and at any time only one of this
others will be selected okay fine that
is right now a 7 is used here a 6 is
used here individually whereas a not FA
collectively are used in other words
here this a not efi code will have to be
decoded to get a D address whereas here
directly a 7 is given and a 6 is given
now you have to recall here once
whatever I was talking about earlier say
are always talking about whenever you
have a code a then you can
do a linear selection that is using one
bit of these of the code at a time or
you can use the entire n bit code and
decode and get so there are two
procedures we were talking about earlier
remember that is use a decode procedure
and make use of an N bit code or each
one bit of the N bit code you use so
that is what you are seeing here
precisely so linear selection is used
while in your selection I was also
mentioning one bit at a time only one
bit at a time that is why if you have a
7 as well as a 6 both are one so suppose
you have a an address right let us say a
7 a six fi to a not okay suppose you
have an address like 1 0 whatever it is
and then another address 0 1 whatever be
the address okay not too Fi and say
another address 0 0 okay some address
okay it is going to be refer to some
specific location and then another one
now look at these four combinations
specifically we concentrate on a7 and a6
so when a 7 is 1 a 6 is 0 this is going
to be selected so depending on some code
n or TFI one specific address one
specific location this will be addressed
when a7 is 0 and a 6 is 1 so this will
not be selected this will be selected
and which specific location depends on
that particular address N or the effect
whatever it may be 0 0 none of them
selected so no memory location at this
now what happens a 7 a 6 both are
selected okay
both are selected
sometimes it may be permitted in some
cases it may not be permitted for
instance suppose this CPU requires an
8-bit data okay suppose this requires an
8-bit data and 8-bit data and if these
memory locations are going to say output
8-bit data both of the ok Here I am not
showing that let us say that also is
outputting an 8-bit data then what
happens both of them will be outputting
8-bit data and the CP is going to see
that means there is going to be a clash
if both a 7 a 6 or 1 1 that is both are
getting selected suppose this is a
16-bit CPU assuming and these continue
to give only 8-bit data then possibly I
can organize this to give the low byte
and the other one hybrid in which case
no problem so in some cases this
combination is permitted in some other
cases it will not be permitted anyway
our point here is to note that the
address lines can be used in both ways
that is either you can have a bunch of
address bits and then decode them and
use them or use each one of those
address bits and do and select different
parts of the memory in a linear select
manner so body things are in use okay
now that is as far as the addressing
part is concerned now there is one other
point which I would like to mention
before I go into discussion of something
else it's this when we talk about memory
there are two things we may talk about
one is memory system or subsystem as a
whole okay
and another one is the say the
components in that say for instance
memory
okay that constitutes the memory
subsystems so essentially the memory
chips for instance this may be a memory
chip this is another memory chip and so
on okay fine now together with these
chips which hold the memory data that is
the data in the memory plus the
controller all these things will form
the memory system okay so the CPU looks
at the memory system as a whole which
consists of different chips now suppose
we have say a memory system of capacity
we talk about a capacity a capacity say
four kilo bytes okay that is a bike
capital D is four byte four kilo bytes
now there are many ways in which you may
be able to organize this particular one
how functions you can have four K
addresses right and each address is
giving out one byte data this is one
possibility they are another thing that
is eight bits in other words what I am
talking about is 4 K by instead of by
talk about eight bits
or the other way fine
the total capacity of it is 4k by we may
have 4k addresses each of one byte
the other thing is you may have
functions to K and the says each of two
bytes or in other words 16 bits many
ways in which we can organize our also
instead of 4k by one byte you can also
have 8k of four bits in a 4k by eight
bits we can have 8k of four bits also
now all these things well finally would
mean from the CP point of view 4 KB
memory system that's all right ok
generally whenever we talk about
capacity of the system it will be
indicated in terms of so many bytes
whereas when it comes to talking about
the capacity of the chip and the chip
level generally it is at the bit level
it is what you would find in the data
sheets ok so anywhere you see capacity
the system it will be done at the byte
level for instance we can say right
suppose we have a chip of 1 kilo bits
okay one kilo bits
one kilo bits then this means basically
suppose we have a chip of capacity 1
kilo bits and we want using this chip we
want to construct a memory system of 4
kilo bytes
so from this you can see we do not know
here these 1 kilo bits how its organized
we have got to see basically possibly a
it is organized like ok 1k know there
are 256 locations of 4 bits each let us
assume here also there can be many
variation for instance you can also have
1k of 1 bit also it is also possible
right
anything is possible right if I have to
this particular chip capacity is 1k bits
which is actually to 256 before bits
basically it means this chip has 256
locations from each location I can get
the data of size 4 bits now if using
this chip I want to construct 4 kilo
byte memory system so here I need a byte
organized memory and so for byte
organization I need to search chips okay
with two such chips I will get 8 bit
output which is a byte output so with
two such chips I only have as many as
256 locations and what do I want I want
4 kilo locations so 256 into 4 will be 1
KB that means with 8 chips I can get 1
KB so 8 into 4 with 32 chips right 32
chips of that I can have
it is 32 chips I can have this memory
system of 4 KB fine
so this is what we have to remember
whenever we talk about the chip it will
usually be referred to in terms of bits
and whenever we talk about system it
will be in terms of bytes and the memory
system may be organized in many ways the
same way chips also may be giving output
of different sizes right good so 32
chips are they in this particular memory
system fine I think that's about the CPU
memory interaction now we will go into
some detail about whatever we had talked
about earlier the CPU always addresses
directly I said earlier ok the previous
lecture the CPU addresses directly the
one part of memory which will be the
fastest one because then only the
processor utilization is the highest so
what are we have been talking about is
usually the one which is closest to the
CPU ok there will be other centrioles
which will be coming with other parts of
the memory system okay now CPU always
places an address and that address will
be decoded and then the contents from
that part of your address will be sought
first from the cache memory right
we will talk noted earlier just to
revise we are talking about three levels
of memory no cache memory the second one
will be the main memory because the main
memory usually consists of dynamic Ram
we also just refer it as DRAM memory and
the third level of memory is not really
memory but it is storage so usually it
is disk or mac tape
okay so I'll just call it a storage
system now this is very fast because it
is very fast the cache memory will
always consists of chips which will be
very fast because it is very fast it is
always costly and because it is always
costly the size of that also will be the
least okay so just let us say we have 1k
of cache memory then let me talk about
Venice when we say 1k we mean 1k bite
generally because it is by dog
measurement the DRAM let us say is 4 K
or 16 K or something like that and here
it can be more also okay just orbital
everything talking about here it makes
me some mega or Giga and so on so forth
okay so in terms of mega or Giga we talk
about whatever it is so the CPU
addresses the memory and looks for
whether well you know when we talk about
a program what is the program address
that would correspond to the address of
this CPU whatever the CPU can handle
okay let us assume the CPU has a 20-bit
address 20-bit address will correspond
to two double 20 that is 1 mega okay so
one megabyte address if you assume a
byte address ability one megabyte that
is what the address ability of it right
now
where is one megabyte and where is 1k or
16 K so the CPU can address as much as
one megabyte but in DRAM or the cache we
have far less space which means
assuming there is a program which
possibly we need not be as much as one
megabyte but when the programmer lights
he'll be writing him he knows that it is
a 20-bit address the cpu can handle and
so he will be generating a 20-bit
address okay but he does not know the
internal arrangements fine
so a 20-bit address may be generated but
it shall have to be translated into some
lower size of the memory okay good which
means assuming okay just assume there is
a program of size 1 mega itself then
when we have a cache when we say CPU
addresses or accesses only cash normally
it accesses only one key block so 1k of
that 1 Meg now it is possible that the
CPU places an address and it does not
find that particular data which it wants
here because any time this is going to
have only one K of the total 1 min so
next thing the cache if that particular
thing is not available in the cache the
data is not level with the cache it
allowed to be looked for in the next
level which not available there it will
have to come from here remember that the
CPU will deal only with this the CPU
will not start looking for in the DRAM
or storage or anything then what what
happens if that happens what does it
mean the processor utilization will come
down is it not so there must be some
extra circuitry right
the CPU we look for this which not there
some other circuit will take care of
moving the required information the
block of data from here to here so we
always talk about something like a block
of data we
or which can be moved from one level to
the other level okay so now this block
of data for instance here we are talking
about a 1k block there okay a block of
data what is it which will be moved okay
so this is the minimum unit of data this
entire one can need not be a block okay
there is a minimum unit of data that is
passed between two levels whenever
something is not available okay when we
say that between any two levels okay
normally we will be having a different
set of issues when we have when you have
to move this block of data from DRAM to
cache memory or from storage to deira
okay there are different issues here
first we will take up this particular
one so CPU looks for some data right in
the cache it is not available then the
cache must get that particular block of
data from the d-damn agreed right
this cash also will not be organized as
1k full block okay we will see that we
will see that when we discuss the detail
okay
suddenly a decision must be taken to see
which of the existing contents in the
cache can be moved away because when we
say we are move something from the DRAM
then something must be moved out of cash
right the same set of issues exists here
also because essentially we have 1k and
let us say the 1k is full but then CPU
does not find what it wants in the drunk
case so something must be removed and
then whatever is required must be moved
in this is one specific issue the same
thing holds good from here to here holds
okay so how this particular thing is
organized we are going to see now as
long as the CPU finds what it wants in
cache then we say the CPU has hit okay
that is CPU addresses and gets the data
then we say this situation is called the
heat when they whenever the CPU looks
for the data it does not find it then we
call it as miss that is the CPU misses
the data or CPU gets the data and
proceeds it is processing further and if
CPU hits and gets it no problem but when
CPU misses then there is a specific miss
penalty time we are going to work out
now this penalty associated with the
missing must be kept as low as possible
why then only the processor can be
utilized well so we will go into these
details in the next lecture
you