BiCMOS Driver;BiCMOS 32-bit Adder - Electrical Engineering Video Lecture - Electrical Engineering (EE)

Oh
so we shall continue our discussion on
by CMOS logic circuits and keep
comparing their performance with respect
to CMOS and see how it actually is an
improvement on CMOS in quite a number of
applications so before we do that let us
see how in a CMOS environment okay one
would drive a large capacitive load okay
because we have already seen that a bi
CMOS would be an advantage if we are
driving a large capacitance capacitive
load because the delay does not increase
at the same rate as it does in the case
of a CMOS so first if you want to really
actually make a comparison we have to
see how you use a CMOS to drive a
capacitive load so this is a CMOS
inverter okay now suppose I just before
we go into that let us take up a small
example you have a CMOS inverter driving
a similar CMOS inverter okay that is you
have an inverter now if suppose the
delay of this first inverter okay is
given by cows okay okay
now suppose I suppose we increase the
widths of all the transistors in this
circuit okay that is therefore
transistors by a factor alpha say okay
that is we make this whatever is the
width of this transistors we increase
them all the four transistors what is
going to be the new delay this is now
going to be changed or is it going to
remain the same that is the question now
you see that what happens to the
capacitance
as seen by the first inverter the
capacitance goes up by a factor alpha
okay
and you know that the delay okay this
tau is proportional to we have all we
have seen in all the expressions that it
is dependent on the load capacitance by
the trans conductance parameter
okay now this CL is proportional to W
into L ratios okay so this one will be
again proportional to W into L okay and
K is proportional to W by else okay so
you see that what is going to happen is
if you increase the widths of all the
transistors well see L refers to the
capacitor input capacitance of this
channel of this inverter that is going
to go up because W has gone up okay and
the K factor or the trans conductance
parameter of the driving transistor okay
that also goes up by the same factor
with the result that the delay remains
unchanged okay that is again if you
increase the widths of all the
transistors by the same amount okay
that toward the delay okay doesn't
change because the capacitance is going
up as well as the driving capacity is
going up the current charging the
capacitance is also going up by the same
amount okay but if it if you take the
lengths of the devices okay suppose you
increase the lengths all the lengths of
the transistors by a factor alpha say
what is going to happen the capacitance
goes up by a factor alpha the current
goes down by a factor alpha okay because
the current charging the capacitance is
proportional to W by L so the delay goes
up by a factor alpha squared
okay so the okay so now in if you look
at it from another angle if you reduce
the length by a factor alpha in fact the
speed is going to go up by a factor
alpha squared because the delay is going
to go down okay by a factor alpha
squared so that is the driving force
behind reducing the
mentions so the lengths of the
transistors must be made as small as
possible okay from the delay point of
view okay now all right so again this is
that tau is the delay for this inverter
if it is driving a similar inverter okay
let us call that delay equal to trap tau
okay now suppose this same inverter okay
the same inverter is driving a
capacitive load CL say okay and suppose
this CL okay is equal to Y times the
scene of this same inverter that is the
input capacitance of the same inverter
okay what is going to be the delay what
has happened is that with capacitance
has gone up by a factor Y okay
so if the delay is tau for driving
capacitance equal to C in okay if you
are driving a capacitance CL obviously
the delay is going to be Y times tau
okay because the delay is proportional
to CL by KK remains the same you had the
same inverter driving a load okay so in
this case the delay is going to be Y
times now okay all right now suppose so
this is a scheme you have as a CMOS
inverter driving a capacitance
capacitive load now let us take another
see how we can in fact reduce this delay
okay now suppose here itself instead of
having this inverter driving the load
directly we have this particular scheme
that is you have inverters a series of
inverters a cascade of inverters okay
all right like this no one inverter like
this then I think I should basically
okay you have an inverter like this then
you have a large number of inverters one
after the other
okay driving this load sphere okay so
this is our original inverter okay and
we make it this way that suppose the
original inverter is like this that is
the P MOS and this is the N Mo's okay
all right
the P Mo's you have the length of the P
Mo's LP and the width is WP okay and the
N Mo's here the length is L n and the
width is w --n okay then the next
inverter what we do is we remain we
retain the same length okay but we make
this width alpha WP and we make the this
with alpha WN okay that is increased by
a factor alpha so what is the delay of
this inverter driving this next inverter
that is alpha times tau okay because
this width the the width of the driving
trans of the transistor it is driving
the the transistors in the invert it is
driving is increased by a factor alpha
we have already seen that so this is
alpha tau the next inverter to say alpha
squared WP and alpha squared
w8 okay now what is the delay of this
inverter the second inverter driving the
third inverter okay here what has
happened is the widths of the
transistors in the third inverter is
alpha times the width of the transistors
in the second inverter okay so again the
delay is going to be alpha
ow okay if this had also been alpha
times W N and alpha times W be the delay
would have been tau itself okay we have
seen that if you have equal weights okay
it is the same tau all right so this is
so if you have n such stages okay
so that Alright alpha times you have n
such stages and alpha to the power n is
equal to Y where Y is what Y is CL by
seen okay so this is alpha times the
capacitance of this input capacitance is
the input capacitance or the second
stage is alpha times this okay the third
one is alpha square times scene okay and
the final CL is going to be alpha times
alpha to the power n times scene okay
that is the capacitance so you have
alpha to the power n if you have n
stages okay you have alpha to the power
n is equal to Y okay where Y is the
ratio of CL to seen okay all right now
so what is the total delay in this case
you have n stages and each stage has a
delay of alpha times tau so the total
delay is n times alpha tau okay so in
this scheme total delay is equal to n
times alpha tau okay so you see that in
this if you have a cascade of inverters
like this the total delay is n times
Alpha Tau whereas if you had we are
driving it directly okay it would have
been y times tau
all right now let us see okay basically
so we will call this the cascade okay
total delay we'll call it a peak tau
cascade okay a cascade of inverters and
our direct
okay so why tau is the delay of the
direct when it is directly driven so tau
cascade by tower direct is equal to n
times alpha tau divided by Y times tau
okay so this and what is in actually and
we know is alpha to the power n is equal
to Y okay so we know that alpha to the
power n is equal to Y so we can write n
lon alpha if you take the lawn on both
sides is equal to lawn why
okay so n is equal to lawn Y by lawn
alpha okay so here we have tau cascade
by tau direct becomes equal to lon y by
lawn alpha ok Tau Alpha by Y okay so
alpha by lawn alpha into on Y by Y okay
so we call this say x times lawn right
bye-bye
see this lawn Y by Y is a constant
depending on the capacitance you are
driving okay if y is y is the ratio of
the load capacitance to the input
capacitance okay which is a constant now
what you have to do in our design we
have to choose the number of inverters
we want to put and the ratio of the
width of the inverters okay that is
their design which we have to take up so
what is going to be that factor alpha
okay that is what we have to see now
obviously what our aim should be to
reduce this as far as possible
okay tau cascade by tau direct should be
as small as possible so we have to
minimize the value of
X okay and what is X alpha by lon alpha
all right so alpha by lon alpha we have
to minimize so we have to put we have to
differentiate this alpha by lon alpha
and put it to zero okay okay so if you
differentiate this alpha by lon alpha
what you get you have on alpha minus
alpha okay all right and which means
that lon alpha is equal to 1 which means
that alpha is equal to e all right so if
this is the case if alpha is equal to e
then what is this tau cascade by tau
direct so X is equal to so alpha is
equal to e so alpha by lon alpha is
equal to e ok alpha is equal to e lon
alpha is equal to 1 so that is going to
be e so basically it becomes e times
lawn wise my Y ok so that is the tau
cascade by tau direct okay
we can take a example okay and see how
much it is effective say suppose let
just we are taking some numbers let Y is
equal to I'm just using an arbitrary
number this two nine eight one is taken
because that is equal to e to the power
8 okay all right so law and why is it
going to be equal to 8 okay
so tau cascade right now direct is going
to be 8 inch by two nine eight one okay
and this is 80 is around 20 1.75 by 2 9
each one so what you see is if you are
using a cascade of inverters okay you
have substantial savings in delay okay
this is less than 1 percent of the delay
you would normally have had if you would
have been direct driving the load
directly okay alright if you had been
driving the load directly using that
CMOS inverter whatever delay you would
have had by having a cascade of
inverters like this the delay is going
to be about even less than one percent
of that delay okay
so usually in a CMOS environment okay
when you are driving large loads okay
you have to use a cascade of inverters
like this especially this type of
circuit is important for example in a
clock circuit in a clock generator
circuit you know that in a large circuit
okay you will have a master clock
somewhere okay and that clock output may
be going to a large different regions in
the circuit okay it is may be driving
different parts of the circuit okay and
so the effective load for that clock
generator is going to be enormous okay
so you will have to have such drivers
for that okay because it is important
because if the delay is too much
basically you have to use
slower clock okay all right you cannot
go for very high frequency clock okay so
in order to reduce the delays okay you
have to go for buffering okay or you use
a cascade of inverters like this all
right with with gradually increasing
dimensions
all right the inverters will have
gradually increasing dimensions so in
this particular case you will have 8
such inverters okay followed by the load
okay and because you have to reduce the
delays okay so on the one hand okay you
are reducing delay but of course you are
paying for it in terms of area okay that
is you require so many inverters not
only that the sizes of the inverters are
gradually increasing so that the last
inverter will be a very big inverter
okay the width of the transistor is
going to be very large because it is
increasing in a geometric fashion okay
all right so so what we shall now do is
we shall see how the bi CMOS okay can be
effective in actually driving such large
loads okay
by saving area okay when compared to the
CMOS counterpart okay you shall take a
small we shall take an example for that
okay and try to understand with that
suppose you have an inverter CMOS
inverters with the different dimensions
are WP is 10 micron
wn7 my son and of course LP is one point
five microns and Ln is 1.5 micron also
this of course as you see that the
lengths of the devices are always kept
at the minimum value okay this we only
play around with the widths
okay because the as we see as we have
seen the delays okay I am mostly
determined by the links okay
all right so and for this inverter okay
suppose it is it has to drive a load
capacitance of Pico farad's okay and
also let us say that this in this CMOS
technology the oxide thickness okay is
given as 225 angstroms
so that is this specified okay 225
angstrom is the oxide thickness okay
these are the dimensions of the devices
this is the load capacitance which it
has to drive now let us we shall see in
our design how many stages of CMOS we
require okay for driving this load and
what are the sizes are the dimensions of
the different transistors okay now so
first what we have to calculate is the
seal l2 see in ratio okay that is the
input capacitance of this particular
inverter okay so we have to take the
total area so what is the total input
area that is WP into LP plus WN into Ln
okay so area is equal to W P into L P
plus WN into Ln okay is equal to so 10
into 1 point 5 is 15 and 7 into 1 point
5 is 10 point 5 so it is 25 point 5
micron square okay
so see in is equal to epsilon a by T ox
what is epsilon for silicon dioxide it
is 3.9 okay into 8.8 5 into 10 to the
power minus 14
okay that is epsilon or not this is
epsilon R okay into area 25 point 5 into
10 to the power minus 8 percent
accredits is in centimeters all all in
CGS units okay
this farad per centimeter this is
centimeter squared okay bye offside
thickness okay 225 angstroms okay 225
into the power minus 8 okay so this
comes to 39 I just give the result 39.3
them to farad okay so if this is 39.3
femto farad so the load capacitance is
given as 2 Pico farad okay
so CL by seams is equal to 2000 by 39.3
this comes to almost fifty ones okay
which also happens to be almost equal to
e to the power 4 okay all right so what
is going to be the dimensions of the
individual transistors okay so the first
one is
okay this is WP this is W in alright so
it this is all 1.5 the lengths do not
change this is all in microns WP is 10
okay slightly wider than WN in this case
okay
seven here WN alright
the next device is going to be e times
all this what we have done is we have
taken that the width of the transistors
is going to be e times increasing by a
factor
II okay all right so this is going to be
going to be wider okay so this is going
to be twenty seven point one eight okay
and this is going to be 19 speed then
the third
okay this is going to be 70 almost
seventy three point nine okay and this
is going to be 52 okay then the next one
is 200 and this is going to be around
140 okay for all the transistors the
lengths are remain same as 1.5 micron so
these are the four stages so from here
to here it is going to be e okay V
squared EQ and the load is again another
II that is e to the power 4 okay so CL
CL by CN is equal to e to the power 4 so
you have this four stages driving the
capacitance alright so just I am quoting
from a report from which I took this
example okay they were driving the same
load and using CMOS okay they had to
fabricate this they required an area of
sixteen thousand six hundred microns
squared and the delay was 1.9
nanoseconds okay they fabricated the
same thing using a single by CMOS
inverter okay where the moss dimensions
we're the same as this first inverter
and they just included a bipolar
transistor just as we had discussed last
class that you have a the CMOS okay with
the with the bipolar transistor by CMOS
inverter normal by CMOS inverter where
the mas dimensions are given by this
smaller smallest device here okay so
this is for CMOS for a bi CMOS
the area required was just 2,500 my
front squared and the delay was 1.4
nanoseconds okay see the game see you
have you are driving a load which is 51
times the input capacitance
now if the bipolar transistor is is able
to give you a current gain of more than
50 okay the same CMOS inverter okay when
you compare with the same CMOS inverter
driving the same load okay you are going
to get a lower delay isn't it so you see
that this in fact gate gives you a lower
delay compared to the CMOS inverter okay
not only that the area requirement is
much smaller because you are using just
the smaller size devices here okay and
you just have extra some bipolar
transistors whereas here you use
progressively larger devices okay and
then which requires a lot of area so
using bi CMOS drivers to drive large
capacitance loads you not only gain in
terms of speed but also you require a
much smaller area okay so that is the
advantage of BI CMOS drivers over CMOS
drivers and it has been it is now being
widely used okay wherever you want to
drive for example in memories for
example after that we shall see that
also after address decoder okay we have
the memory cells to be driven okay so
one so if you have one megabit memory
okay you will have 10 to the power 6
cells okay which may be thousand by
thousand array so the output of our
address decoder must drive thousand
gates okay which means a large
capacitive load okay
and by CMOS driver is obviously going to
be much superior compared to the CMOS
driver okay so there are many
applications okay where you require
large capacitive loads to be driven and
obviously the by
CMOS inverter or bi CMOS driver is going
to be superior in that respect okay
alright so that is the example of a bi
CMOS driver we shall take up some more
examples okay where bi CMOS is used here
what we have taken is the conventional
bi CMOS inverter as a driver okay so
instead of the CMOS inverter you use a
bi CMOS inverter okay or you may use
instead of the CMOS and gate for example
an and gate you may use a bi CMOS NAND
gate okay where the output you have a
transistor which with the help of the
current gain it gives you lower delays
okay but in many other applications okay
it is the judicious use it you do not
use the bi CMOS as such as gates okay
but by the judicious use of bipolar
transistors okay you can increase the
speed of the operation okay
you shall take up one more such case
okay in the case of an adder circuit
alright and we shall see how in
incorporating a bipolar transistor in a
set in an essentially CMOS environment
okay you get higher speed okay so the
next example we shall take up is an
adder circuit so I shall just give you a
brief introduction about adder just
maybe as to remind you okay the carry
look ahead adder I think you are aware
of it but anyway just to give you an
idea what is a carry look ahead adder
okay normally if you have two types of
adders one is called the ripple carry
adder where if you are say for doing a
4-bit additions okay
you have force adders okay and what you
do is you have the inputs to each each
stage okay and it is that
and the output of each added is going to
be the sum and carry outputs okay and
what is going to happen here the sum
output say coming out and the carry
output is going to come in as go to the
next stage okay so it is just rippling
through all the stages okay so if you
have a 32 bit added you know then the
output of this has to go here then the
next will change because of that and so
it is a rippling effect okay and it
takes a long long time okay what a carry
look ahead adder does is it prepares
this carry inputs to each stage
beforehand okay in a very short time so
that the even for the last bit okay the
addition does not take much time okay so
we shall just see what I carry look
ahead adder is and then we shall see how
incorporation of bipolar transistors in
a CMOS environment actually can speed up
the operation okay so basically a full
adder okay which has got three inputs
you know that is the two inputs to be
added and a carry input from that which
comes from the previous stage so a full
adder can be looked constructed using
two half adders okay alright what is a
half adder a half adder has got two
inputs okay and two outputs one is the
sum output and the other is the carry
output okay so if you know that if the
inputs are 0 0 sum is 0 carry 0 if one
input is 1 the other is 0 sum is 1 carry
0 if both inputs are 1 sum is going to
be 0 carry is going to be 1 so basically
the sum output which you have is the
exclusive or function of a and B if we
consider them as two the inputs as a and
B okay and
the carry output is equal to and
function of a and B okay now let me call
this this exclusive or of a and B we
call it the P term okay a exclusive or B
why we call it P has just come to that
and this is called G okay a B so P
stands for propagate and G stands for
generate okay so you have the propagate
term and G is the generate term
okay now you feed this directly to the
next adder okay the carry in which you
have to this stage all right goes in as
the other input to this half adder okay
all right so here at the output you have
sums is equal to exclusive odd so this
half adder again so the sum output here
is going to be the exclusive god of the
two inputs here so this is exclusive or
of a exclusive or B exclusive or of the
carry input okay and here what you feed
is so here again this is going to be the
and function of the two inputs
alright so here you have one of the
input is P and the other input is seen P
seen okay and you take an or of these
two Kerry outputs all right so the carry
output is actually equal to
G plus P into CM okay where G is equal
to and of a and B okay and P is equal to
exclusive or of a and B okay now G is
called generate because it generates a
carry if well it is going to be high if
both a and B is going to be high okay so
it generates a carry if a and B is are
both high that is the inputs to that
present both inputs are high
of course you are going to have a carry
irrespective of carry in or what
whatever alright you are going to have a
carry out so it generates the Cadi
alright so you will have going to have a
carry out if G is high okay
the other case where you can have a
carry is that you had a carry from the
previous bit that is there was a carry
input okay and you are propagating that
caddy okay that is there was a carry
input from the previous in from the
previous bit okay and now if one of the
inputs other inputs a or B is high okay
then you basically propagate that carry
to the next bit okay
so P is going to be high it's an
exclusive odd function so if any a or B
is high you know any of them is high
okay the output is going to be if the P
is going to be high okay alright so if C
in is high and either of a and B is high
that you have the carry output so
basically the carry input is propagated
to the output
okay so P is going to be high if
exclusive are in B is high okay so that
you have a carry output if either you
generate a carry in this present bit or
you propagate whatever carry in Carine
is just propagated to the output if P is
high okay and C in is height then also
you're going to have a carry out so this
is for a particular bit okay you you
have the carry output alright now if you
consider
say a four bit adder okay what you can
do is you can think of it this way so
the input you have c0 is the carry input
input to that four bit adder okay
c1 is equal to so you have the inputs so
for the first bit okay you have a 0 and
B 0 at the inputs okay and basically you
have which gives rise to G 0 and p 0
okay so basically if you have this all
these zeros here okay you'll have p 0
and you'll have G 0 okay everything is
zeroes if it is for a bit 1 okay this
one will be a 1 and B 1 you have G 1 and
P 1 okay where G 1 is a 1 and an
function of a 1 and B 1 and P 1 is
exclusive or of a 1 and B 1 okay so what
is C 1 C 1 is G 0 plus p 0
see in okay that is actually the seam
okay or okay I think we should pull it C
zero which is actually seeing alright
okay this is c1 which goes it as the
input to the first bit okay
c1 is g0 plus p0 c0 okay
so for first bit you have the inputs a1
b1 and c1 okay
bit one okay this forbid 0 so for the
next C 2 will be equal to G 1 plus P 1 C
1 okay and what is C 1 C 1 is G 0 plus p
0 C 0 okay so we can write G 1 plus P 1
into G 0 plus C 0 C 0 okay which means
this is equal to g1 plus p1 g0 plus T 1
P naught C ok all right so you can see
the logic here that C 2 that is the
carry there is going to be a carry
output or the carry input to the B 2 if
there is a carry generated at bit 1 or
there was a carry generated at bit 0
which got propagated through p1 or there
was an input carry which got propagated
through both P naught and P 1 all right
so that is how you get C 2 similarly you
will get C 3 okay I can do it the same
way it will be G 2 plus P 2 C 2 and then
you instead of C 2 you write the same
thing okay so what do you get you will
get G 2 plus
P 2 G 1 plus P 2 P 1 G naught plus P 2 P
1 P naught C 0 ok
similarly C 4 you will get as g3 I'm
just writing it down okay plus p3 g2
plus p p3 p2 g1 plus p3 p2 p1 G not p3
p2 p1 b not C all right so these are the
terms so the interesting thing here is
that what you can do you already know
these things ok so you can instead of c4
you see in if it was a ripple-carry you
have to go through all the stages before
you do it but here you can generate
these things so basically the scheme
which you are going to have now is
you are going to have suppose what what
we do is suppose we have a 32-bit adder
okay what is done is see if you have a
32-bit adder it is this is going to
become a very cumbersome expression to
do it okay so you break it up into say
eight 4-bit adders carry look ahead
adders so you have one four bit carry
look ahead adder okay so here you have
the inputs say a zero to a four and
sorry a zero to a 3 and B 0 to B 3 okay
and you have the outputs s 0 to 3 so C 0
comes in here okay and C 4 goes out okay
and then this is another carry look
ahead adder okay where you have the
inputs a 4 to a 7 b4 through b7 okay and
you have the outputs S 4 to 7 and C 8
goes out so basically this is the 4 bit
carry look ahead adder all right and
then you are going to have 8 such carry
look ahead adders alright and so what is
the critical path in this circuit it the
critical path is this this transmission
of this carry look-ahead carry okay it
has to go from C 0 so to the 8 adder or
this 8 4 bit carry look ahead adder so
only once only when this is available
made available to that carry look ahead
adder okay can that output be a valid
one ok so this is the critical path for
this carry look ahead adder and this
must be properly designed because the
total delay of the 4 bit carry look
ahead adder is going to depend on this
path ok how fast this is okay so
basically if you look at it this way
the four bit carry look ahead adder okay
will consist off I just draw it like
this
you have four half adders okay so you
have a not b not fed here a1 b1 said
here a 2 B 2 fed here
a3 and b3 third gear
okay and what is coming out of this half
adders you have the T's and G's alright
you have here you have P naught and G
naught here you are looking to have P 1
and G 1 P 2 and G 2 and P 3 and G 3 okay
so all this is going as input okay to
what is called a carry propagation
circuit so this is the carry propagation
circuit okay which has a input C naught
okay and passes out C 4 which is going
to be used by the next four bit carry
look ahead adder okay and then and this
as we have seen that in order to
evaluate C 4 what you require as inputs
if you look at this expression here what
you require as inputs is C naught okay
as well as all the G's and peas so if
this is available you can generate C 4
okay so that is what it requires at the
input then you have another circuit okay
which is called the carry generation
circuit okay so the which basically
generates the carries for the different
bits in this four four bit carry look
ahead adder so you are going to generate
the carry that is C 1 C 2 C 3 alright so
as well as of course you require C
naught also so what you do is so this
requires as inputs what what does it
require as input it requires input as C
naught it is required okay again C
naught is required and the different
peas and G's okay up to that stage so
again you know you have the different
peas and G is coming to this circuit
also alright and
you have seen not also coming here okay
and what you get out of this circuit is
you'll have the different carries C
naught C 1 C 2 and C 3 okay
and this then you have another half
adder another Bank of four half adders
okay this is another set of four half
adders which you have okay one not okay
and these half adders
okay required as input the peas and the
C's okay we have seen seen the model for
a full adder okay where some is equal to
exclusive R of P and C okay P where P is
again the exclusive or of a and B that
is already available so this is going to
give you s not okay again for this a
half adder you have the inputs P 1 and C
1 is required so s is equal to exclusive
R of P 1 and C 1 basically you just
require the exclusive are here ok
because the carrion is here ok so you
have s naught s 1 s 2 so this again the
peas are extended up to this okay so you
have s 1 s 2 s 3 so this is a four bit
carry look ahead adder where you have
the input C naught okay you're getting
the and all the inputs the input bits a
not to F a 3 and B naught 2 B 3 and what
you are getting at the output is s
naught s 1 s 2 s 3 ok and the output
carry c4 ok now as we said now this in
this part of the circuit what the
crucial part of the circuit which is
gives rise to the delay is the carry
propagation circuit because what it is
doing is it is taking the carry in and
it is passing out the carry okay here
the carry generation circuit is actually
a
set of this particular circuit you can
say all right because if you look at the
expressions you know C 1 C 2 C 3 it is
it is a simpler expression compared to C
4 and you are just using the same things
all the peas and G's and the C knots
okay so the in this part of the circuit
you have two half adders okay and then
you have the two carry propagation
circuit and the carry generation circuit
the delays in the carry generation
circuits that is C naught C naught is
already there C 1 C 2 C 3 okay that is
going to obviously like take less time
that C 4
okay all right and C 4 is very crucial
because as we have seen that in a 32-bit
adder you you are going to have 8 such 4
bit carry look ahead adders and the
delay the C 4 has to go in as the next
to the next 4-bit adder and as the input
of the carry propagation circuit of the
next 4-bit adder and you will generate C
8 which has to be passed down to the
next 4-bit adder to generate C 12 and so
on okay so this is the most crucial part
in say a 32-bit adder how fast you can
generate this carry propagation circuit
how fast you can generate the carry in
this carry propagation circuit okay well
in a in a CMOS environment okay we shall
see now in the next class we shall see
how it this is generated in a CMOS
environment okay and how you can improve
the circuit or they basically reduce the
delay by using bipolar transistors okay
to create a bi CMOS type carry
propagation circuit okay and we shall
see that by just using very few bipolar
transistors it is not that you are
having a you know you are replacing a
CMOS NAND gate by a bi CMOS NAND gate or
a CMOS inverter by a bi CMOS inverter
but by the judicious introduction of
bipolar transistors you can you can
improve the delays okay all right so it
is you have to
see where you have you want to introduce
that bipolar transistors and how it can
improve the speed alright so we shall
take that up in the next class
you