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All questions of Testing of Embedded System for Computer Science Engineering (CSE) Exam

 Which of the following can compute the exact number of clock cycles required to run an application?
  • a)
    layout model
  • b)
    coarse-grained model
  • c)
    fine-grained model
  • d)
    register-transaction model
Correct answer is option 'C'. Can you explain this answer?

Explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.

Which is a top-down method of analyzing risks?
  • a)
    FTA
  • b)
    FMEA
  • c)
    Hazards
  • d)
    Damages
Correct answer is option 'A'. Can you explain this answer?

Soumya Dey answered
Explanation: The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with a damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.

Which analysis uses the graphical representation of hazards?
  • a)
    Power model
  • b)
    FTA
  • c)
    FMEA
  • d)
    First power model
Correct answer is option 'B'. Can you explain this answer?

Naina Sharma answered
Introduction:
In the field of system reliability and safety analysis, graphical representation plays a crucial role in understanding and analyzing hazards. It helps in visually representing the relationships between various components and events that contribute to the occurrence of hazards. Among the given options, the analysis that extensively uses graphical representation of hazards is Fault Tree Analysis (FTA).

Fault Tree Analysis (FTA):
Definition:
Fault Tree Analysis (FTA) is a systematic and graphical approach used to analyze and understand the causes and consequences of system failures or hazards. It involves constructing a fault tree diagram, which is a logical and graphical representation of the events and conditions that lead to the occurrence of a hazard.

Graphical Representation of Hazards:
Fault Tree Diagram:
In Fault Tree Analysis, hazards are represented using a fault tree diagram. It is a top-down graphical representation that starts with the identified hazard or top event and then identifies all the contributing events and conditions that can lead to the occurrence of that hazard.

Components of Fault Tree Diagram:
A fault tree diagram consists of the following components:

1. Top Event or Hazard: It represents the undesired event or hazard that is being analyzed.
2. Basic Events: These are the lowest level events or conditions that directly contribute to the occurrence of the top event.
3. Intermediate Events: These events represent the logical combinations or relationships between basic events and other intermediate events.
4. Gates: Gates are used to depict the logical relationships between events. There are three types of gates used in fault tree diagrams - AND gate, OR gate, and NOT gate.

Analysis Process:
The analysis process in Fault Tree Analysis involves the following steps:

1. Identify the Top Event: Determine the undesired event or hazard that needs to be analyzed.
2. Identify Basic Events: Identify the lowest level events or conditions that contribute to the occurrence of the top event.
3. Construct the Fault Tree Diagram: Use the identified events and conditions to construct a fault tree diagram using appropriate gates.
4. Analyze the Fault Tree: Analyze the fault tree diagram to determine the causes and consequences of the top event. This can involve calculating probabilities, identifying critical events, and evaluating the effectiveness of safety measures.
5. Mitigation and Prevention: Based on the analysis results, develop strategies and measures to mitigate or prevent the occurrence of the top event.

Conclusion:
In conclusion, Fault Tree Analysis (FTA) is the analysis technique that extensively uses graphical representation of hazards. Its fault tree diagram provides a visual representation of the events and conditions that contribute to the occurrence of a hazard, making it easier to analyze and understand the causes and consequences of system failures or hazards.

Which gate is used in the geometrical representation, if a single event causes hazards?
  • a)
    AND
  • b)
    NOT
  • c)
    NAND
  • d)
    OR
Correct answer is option 'D'. Can you explain this answer?

Explanation: The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation, if several events cause hazards.

 Which gate is used in the graphical representation, if several events cause hazard?
  • a)
    OR
  • b)
    NOT
  • c)
    AND
  • d)
    NAND
Correct answer is option 'C'. Can you explain this answer?

Rishabh Pillai answered
AND gate is used in the graphical representation when several events cause hazard:
- Explanation:
- AND gate:
- In the context of hazard analysis in digital circuits, an AND gate is used when multiple events need to occur simultaneously to cause a hazard.
- An AND gate outputs a high signal only when all of its input signals are high, representing the concept that all the contributing events must be present for a hazard to occur.
- Several events causing hazard:
- When there are multiple conditions or events that, when combined, can lead to a hazard, an AND gate is used to represent this scenario.
- Each input of the AND gate corresponds to a specific event or condition that contributes to the overall hazard.
- The AND gate ensures that the hazard is triggered only when all the contributing events are present simultaneously.
- Example:
- For instance, in a safety-critical system, a hazard may occur only when the temperature exceeds a certain threshold, the pressure reaches a critical level, and a specific sensor fails. In this case, an AND gate would be used to combine these conditions.
- Conclusion:
- By using an AND gate in the graphical representation of hazards caused by several events, designers can model complex scenarios where multiple factors need to align for a hazardous situation to arise.

What is FSM?
  • a)
    Fourier state machine
  • b)
    finite state machine
  • c)
    fast state machine
  • d)
    free state machine
Correct answer is option 'B'. Can you explain this answer?

Hiral Nair answered
Explanation: The FSM is the finite state machine. It will be having a finite number of states and is used to design both the sequential logic circuit and the computer programs. It can be used for testing the scan design in the testing techniques.

 Which formal verification technique consists of Boolean formula?
  • a)
    HOL
  • b)
    FOL
  • c)
    Propositional logic
  • d)
    Both HOL and FOL
Correct answer is option 'C'. Can you explain this answer?

Explanation: The propositional logic technique is having the boolean formulas and the boolean function. The tools used in propositional logic is the tautology checker or the equivalence checker which in turn uses the binary decision diagrams which is also known as BDD.

 What is HOL?
  • a)
    higher order logic
  • b)
    higher order last
  • c)
    highly organised logic
  • d)
    higher order less
Correct answer is option 'A'. Can you explain this answer?

Preethi Iyer answered
Explanation: The formal verification techniques are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The HOL is the abbreviation of the higher order logic in which the proofs are automated and manually done with some proof support.

What is meant by FOL?
  • a)
    free order logic
  • b)
    fast order logic
  • c)
    false order logic
  • d)
    first order logic
Correct answer is option 'D'. Can you explain this answer?

Saanvi Bajaj answered
Explanation: Many formal verification techniques are used and these are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The FOL is the abbreviated form of the first order logic which includes the quantification.

Which of the following is also known as boundary scan?
  • a)
    test pattern
  • b)
    JTAG
  • c)
    FSM
  • d)
    CRC
Correct answer is option 'B'. Can you explain this answer?

Partho Joshi answered
Explanation: The JTAG is a technique for connecting scan chains of several chips and is also known as boundary scan.

 Which of the following is based on fault models?
  • a)
    alpha-numeric pattern
  • b)
    test pattern
  • c)
    bit pattern
  • d)
    parity pattern
Correct answer is option 'B'. Can you explain this answer?

Alok Desai answered
Explanation: The test pattern generation is normally based on the fault models and this model is also known as the stuck-at model. The test pattern is based on certain assumption, that is why it is called as the stuck-at model.

 Which of the following is a popular system for model checking?
  • a)
    HOL
  • b)
    FOL
  • c)
    BDD
  • d)
    EMC
Correct answer is option 'D'. Can you explain this answer?

Explanation: The EMC-system is developed by Clark and it describes the CTL formulas, which is the computational tree logics.

Which is also called stuck-at model?
  • a)
    byte pattern
  • b)
    parity pattern
  • c)
    bit pattern
  • d)
    test pattern
Correct answer is option 'D'. Can you explain this answer?

Prateek Khanna answered
Explanation: The test pattern generation is basically based on the fault models and this type of model is also known as the stuck-at model. These test patterns are based on certain assumption, hence it is known as the stuck-at model.

How is the quality of the test pattern evaluated?
  • a)
    fault coverage
  • b)
    test pattern
  • c)
    size of the test pattern
  • d)
    number of errors
Correct answer is option 'A'. Can you explain this answer?

Snehal Desai answered
Explanation: The quality of the test pattern can be evaluated on the basis of the fault coverage. It is the percentage of potential faults that can be found for a given test pattern set, that is fault coverage equals the number of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.

Which of the following is possible to locate errors in the specification of the future bus protocol?
  • a)
    EMC
  • b)
    HOL
  • c)
    BDD
  • d)
    FOL
Correct answer is option 'C'. Can you explain this answer?

Nilesh Saha answered
Explanation: The model checking was developed using the binary decision diagram and the BDD and it was possible to locate errors in the specification of the future bus protocol.

What is FTA?
  • a)
    free tree analysis
  • b)
    fault tree analysis
  • c)
    fault top analysis
  • d)
    free top analysis
Correct answer is option 'B'. Can you explain this answer?

Saikat Basu answered
Explanation: The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with a damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.

Which is applied to a manufactured system?
  • a)
    bit pattern
  • b)
    parity pattern
  • c)
    test pattern
  • d)
    byte pattern
Correct answer is option 'C'. Can you explain this answer?

Explanation: For testing any devices or embedded systems, we use some sort of selected inputs which is known as the test pattern and observe the output and is compared with the expected output. This test patterns are normally applied to the manufactured systems.

What is CRC?
  • a)
    code reducing check
  • b)
    counter reducing check
  • c)
    counting redundancy check
  • d)
    cyclic redundancy check
Correct answer is option 'D'. Can you explain this answer?

Dishani Bajaj answered
Explanation: The CRC or the cyclic redundancy check is the error detecting code which is commonly used in the storage device and the digital networks.

What is FMEA?
  • a)
    fast mode and effect analysis
  • b)
    front mode and effect analysis
  • c)
    false mode and effect analysis
  • d)
    failure mode and effect analysis
Correct answer is option 'D'. Can you explain this answer?

Samarth Ghosh answered
Explanation: The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.

 What is CTL?
  • a)
    computational tree logic
  • b)
    code tree logic
  • c)
    cpu tree logic
  • d)
    computer tree logic
Correct answer is option 'A'. Can you explain this answer?

Explanation: The EMC-system is a popular system for model checking which is developed by Clark that describes the CTL formulas, which is also known as computational tree logics. The CTL consist of two parts, a path quantifier, and a state quantifier.

Which of the following is also known as equivalence checker?
  • a)
    BDD
  • b)
    FOL
  • c)
    Tautology checker
  • d)
    HOL
Correct answer is option 'C'. Can you explain this answer?

Rishika Pillai answered
Explanation: The propositional logic technique consists of the boolean formulas and the boolean function. The tools used in this type of logic is the tautology checker or the equivalence checker which in turn uses the BDD or the binary decision diagrams.

What does BILBO stand for?
  • a)
    built-in logic block observer
  • b)
    bounded input bounded output
  • c)
    built-in loading block observer
  • d)
    built-in local block observer
Correct answer is option 'A'. Can you explain this answer?

Explanation: The BILBO or the built-in logic block observer is proposed as a circuit combining, test response compaction, test pattern generation, and serial input/output capabilities.

Which of the following is a set of specially selected input patterns?
  • a)
    test pattern
  • b)
    debugger pattern
  • c)
    bit pattern
  • d)
    byte pattern
Correct answer is option 'A'. Can you explain this answer?

Pritam Goyal answered
Explanation: While testing any devices or embedded systems, we apply some selected inputs which is known as the test pattern and observe the output. This output is compared with the expected output. The test patterns are normally applied to the already manufactured systems.

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