All questions of Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam
Which of the following is not involved in a memory write operation?- a)MAR
- b)PC
- c)MDR
- d)data bus
Correct answer is option 'B'. Can you explain this answer?
Which of the following is not involved in a memory write operation?
a)
MAR
b)
PC
c)
MDR
d)
data bus
|
Ravi Singh answered |
Program counter register used to read the value or instruction not in write operation. For write operation MAR, IR and MDR registers are used.
Consider a three word machine instructionADD A[R0], @BThe first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand(source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words,respectively. The first word of the instruction specifies the opcode, the index register designation and the source anddestination addressing modes. During execution of ADD instruction, the two operands are added and stored in thedestination (first operand).The number of memory cycles needed during the execution cycle of the instruction is:- a)3
- b)4
- c)5
- d)6
Correct answer is option 'B'. Can you explain this answer?
Consider a three word machine instruction
ADD A[R0], @B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand(source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words,respectively. The first word of the instruction specifies the opcode, the index register designation and the source anddestination addressing modes. During execution of ADD instruction, the two operands are added and stored in thedestination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is:
a)
3
b)
4
c)
5
d)
6
|
Neha Choudhury answered |
In Indexed addressing mode, the base address is already in the instruction i.e A and to fetch the index data from R0 no memory access is required because it’s a register. So, to fetch the operand only 1 memory cycle is required.
Indirect Addressing mode requires 2 memory cycles only.
Suppose a cache is 10 times faster than main memory and suppose that the cache can be used 70% of the time. How much speed up do we gain by using the cache?- a)0.37
- b)2.7
- c)3.7
- d)0.27
Correct answer is option 'B'. Can you explain this answer?
Suppose a cache is 10 times faster than main memory and suppose that the cache can be used 70% of the time. How much speed up do we gain by using the cache?
a)
0.37
b)
2.7
c)
3.7
d)
0.27
|
|
Ravi Singh answered |
In Flynn’s classification arrays and vectors belongs to SIMD architecture.
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.- a)22
- b)23
- c)24
- d)25
Correct answer is option 'B'. Can you explain this answer?
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.
a)
22
b)
23
c)
24
d)
25
|
Shraddha Iyer answered |
Next Address Field = 7 Bits
ALU Function Field is of 4 Bits (to select possible 1 of 13 ALU fns)
Register-in and Register-out Fields of 3 Bits each Shifter Field of 2 bits to select 1 out of three possibilities:
Auxiliary Field of 4 Bits
Total Bits in μ-instruction
= 7 + 4 + 3 + 3 + 2 + 4 = 23
Register-in and Register-out Fields of 3 Bits each Shifter Field of 2 bits to select 1 out of three possibilities:
Auxiliary Field of 4 Bits
Total Bits in μ-instruction
= 7 + 4 + 3 + 3 + 2 + 4 = 23
The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is- a)55 ns
- b)45 ns
- c)90 ns
- d)19 ns
Correct answer is option 'D'. Can you explain this answer?
The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is
a)
55 ns
b)
45 ns
c)
90 ns
d)
19 ns
|
|
Ravi Singh answered |
Average memory access time = Hit Ratio x Cache access time + Miss Ratio x Memory access time
= 0.90 x 10 ns + 0.10 x 100 ns
= 9 ns + 10 ns = 19 ns
= 0.90 x 10 ns + 0.10 x 100 ns
= 9 ns + 10 ns = 19 ns
When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations- a)1, 2, 3
- b)2
- c)1, 3
- d)2, 3
Correct answer is option 'D'. Can you explain this answer?
When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a)
1, 2, 3
b)
2
c)
1, 3
d)
2, 3
|
Yash Patel answered |
In the case of, auto increment the increment is done afterward and in auto decrement the decrement is done first.
The correct matching for the following pairs is:
(A) DMA I/O (1) High speed RAM
(B) Cache (2) Disk
(C) Interrupt I/O (3) Printer
(D) Condition Code Register (4) ALU
- a)A-4 B-3 C-1 D-2
- b)A-2 B-1 C-3 D-4
- c)A-4 B-3 C-2 D-1
- d)A-2 B-3 C-4 D-1
Correct answer is option 'B'. Can you explain this answer?
The correct matching for the following pairs is:
(A) DMA I/O (1) High speed RAM
(B) Cache (2) Disk
(C) Interrupt I/O (3) Printer
(D) Condition Code Register (4) ALU
(A) DMA I/O (1) High speed RAM
(B) Cache (2) Disk
(C) Interrupt I/O (3) Printer
(D) Condition Code Register (4) ALU
a)
A-4 B-3 C-1 D-2
b)
A-2 B-1 C-3 D-4
c)
A-4 B-3 C-2 D-1
d)
A-2 B-3 C-4 D-1
|
Machine Experts answered |
Explanation:
- DMA I/O (1) High speed RAM: DMA (Direct Memory Access) is used for transferring data between peripherals and memory without involving the CPU. It is commonly used for high-speed data transfers to and from high-speed RAM.
- Cache (2) Disk: Cache memory is a small, fast type of volatile computer memory used to temporarily store data that is frequently accessed. It helps in reducing the access time to data stored on slower storage devices like disks.
- Interrupt I/O (3) Printer: Interrupt I/O involves the use of interrupts to signal the CPU that a peripheral device needs attention. This is commonly used for devices like printers where the CPU needs to be informed when data is ready to be printed.
- Condition Code Register (4) ALU: The Condition Code Register (CCR) is a register used to store the condition codes generated by the ALU (Arithmetic Logic Unit) during arithmetic and logical operations. These codes are used to determine the outcome of operations and make decisions based on them.
- DMA I/O (1) High speed RAM: DMA (Direct Memory Access) is used for transferring data between peripherals and memory without involving the CPU. It is commonly used for high-speed data transfers to and from high-speed RAM.
- Cache (2) Disk: Cache memory is a small, fast type of volatile computer memory used to temporarily store data that is frequently accessed. It helps in reducing the access time to data stored on slower storage devices like disks.
- Interrupt I/O (3) Printer: Interrupt I/O involves the use of interrupts to signal the CPU that a peripheral device needs attention. This is commonly used for devices like printers where the CPU needs to be informed when data is ready to be printed.
- Condition Code Register (4) ALU: The Condition Code Register (CCR) is a register used to store the condition codes generated by the ALU (Arithmetic Logic Unit) during arithmetic and logical operations. These codes are used to determine the outcome of operations and make decisions based on them.
What does CSA stands for?- a)Computer Service Architecture
- b)Computer Speed Addition
- c)Carry Save Addition
- d)None of the mentioned
Correct answer is option 'B'. Can you explain this answer?
What does CSA stands for?
a)
Computer Service Architecture
b)
Computer Speed Addition
c)
Carry Save Addition
d)
None of the mentioned
|
Sudhir Patel answered |
The CSA is used to speed up the addition of multiplicands.
In four-address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)- a)9
- b)13
- c)14
- d)12
Correct answer is option 'B'. Can you explain this answer?
In four-address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)
a)
9
b)
13
c)
14
d)
12
|
|
Mahi Yadav answered |
Four address instruction format:
Consider the following situation and fill in the blanks:The computer starts the tape moving by issuing a command: the processor then monitors the status of the tape by means of a _____. When the tape is in the correct position, the processor issues a _______.- a)Data input, status, data output command
- b)Data input, status control command
- c)Control, status, data output command
- d)Control, status, data input command
Correct answer is option 'C'. Can you explain this answer?
Consider the following situation and fill in the blanks:
The computer starts the tape moving by issuing a command: the processor then monitors the status of the tape by means of a _____. When the tape is in the correct position, the processor issues a _______.
a)
Data input, status, data output command
b)
Data input, status control command
c)
Control, status, data output command
d)
Control, status, data input command
|
Bijoy Sharma answered |
Control command: A control command is issued to activate the peripheral and to inform it what to do.
Status: A status command is used to test various status conditions in the interface and the peripheral.
Data output command causes the interface to respond by transferring data from the bus into one of its register.
Status: A status command is used to test various status conditions in the interface and the peripheral.
Data output command causes the interface to respond by transferring data from the bus into one of its register.
Find out the speed-up ratio between pipelined and non-pipelined system?- a)3
- b)4
- c)3.88
- d)400
Correct answer is option 'C'. Can you explain this answer?
Find out the speed-up ratio between pipelined and non-pipelined system?
a)
3
b)
4
c)
3.88
d)
400
|
Aravind Sengupta answered |
The needed for non pipelined processor
Speedup = 8000/2060 = 3.88
Speedup = 8000/2060 = 3.88
Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed- a)I only
- b)II only
- c)III only
- d)II and III only
Correct answer is option 'C'. Can you explain this answer?
Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
a)
I only
b)
II only
c)
III only
d)
II and III only
|
Moumita Chavan answered |
In auto increment addressing mode, the base address is incremented after operand fetch. This is useful in fetching elements from an array. But this has no effect in self-relocating code (where code can be loaded to any address) as this
works on the basis of an initial base address.
An additional ALU is desirable for better execution especially with pipelining, but never a necessity.
Amount of increment depends on the size of the data item accessed as there is no need to fetch a part of a data.
So, answer must be C only.
works on the basis of an initial base address.
An additional ALU is desirable for better execution especially with pipelining, but never a necessity.
Amount of increment depends on the size of the data item accessed as there is no need to fetch a part of a data.
So, answer must be C only.
A hardware interrupt is- a)Also called an internal interrupt
- b)Also called an external interrupt
- c)An I/O interrupt
- d)A clock interrupt
Correct answer is option 'B'. Can you explain this answer?
A hardware interrupt is
a)
Also called an internal interrupt
b)
Also called an external interrupt
c)
An I/O interrupt
d)
A clock interrupt
|
Roshni Kumar answered |
Introduction:
A hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program and transfer control to a specific interrupt handler routine. It allows the hardware device to communicate with the processor, informing it of events that require immediate attention.
Explanation:
A hardware interrupt can be either internal or external, depending on the source of the interrupt. Let's understand each option in detail:
a) Also called an internal interrupt:
- An internal interrupt, also known as a software interrupt, is generated by the CPU itself.
- It is triggered by a special instruction in the program code that causes the CPU to transfer control to a specific interrupt handler routine.
- Internal interrupts are not directly related to hardware devices, so they do not fall under the category of hardware interrupts.
b) Also called an external interrupt:
- An external interrupt is generated by an external hardware device.
- When a hardware device needs to interrupt the normal execution of a program, it sends a signal to the processor, indicating that an interrupt has occurred.
- The processor then transfers control to the corresponding interrupt handler routine to handle the event.
- External interrupts are directly related to hardware devices and are commonly used for input/output operations, such as keyboard input, mouse input, etc.
c) An I/O interrupt:
- An I/O interrupt is a specific type of hardware interrupt that is generated by input/output devices.
- When an input/output device, such as a disk drive or a network card, completes a task or encounters an error, it can generate an I/O interrupt to inform the processor.
- The processor then interrupts the current program execution and transfers control to the appropriate interrupt handler routine to handle the I/O operation.
d) A clock interrupt:
- A clock interrupt is a specific type of hardware interrupt generated by the system clock or a timer device.
- It is used to keep track of time and schedule tasks.
- The clock interrupt occurs at regular intervals and is used by the operating system to perform various time-related operations, such as updating the system time, scheduling tasks, etc.
Conclusion:
In conclusion, a hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program. An external interrupt, also known as a hardware interrupt, is triggered by an external hardware device and is used for input/output operations. Therefore, the correct answer is option 'B' - Also called an external interrupt.
A hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program and transfer control to a specific interrupt handler routine. It allows the hardware device to communicate with the processor, informing it of events that require immediate attention.
Explanation:
A hardware interrupt can be either internal or external, depending on the source of the interrupt. Let's understand each option in detail:
a) Also called an internal interrupt:
- An internal interrupt, also known as a software interrupt, is generated by the CPU itself.
- It is triggered by a special instruction in the program code that causes the CPU to transfer control to a specific interrupt handler routine.
- Internal interrupts are not directly related to hardware devices, so they do not fall under the category of hardware interrupts.
b) Also called an external interrupt:
- An external interrupt is generated by an external hardware device.
- When a hardware device needs to interrupt the normal execution of a program, it sends a signal to the processor, indicating that an interrupt has occurred.
- The processor then transfers control to the corresponding interrupt handler routine to handle the event.
- External interrupts are directly related to hardware devices and are commonly used for input/output operations, such as keyboard input, mouse input, etc.
c) An I/O interrupt:
- An I/O interrupt is a specific type of hardware interrupt that is generated by input/output devices.
- When an input/output device, such as a disk drive or a network card, completes a task or encounters an error, it can generate an I/O interrupt to inform the processor.
- The processor then interrupts the current program execution and transfers control to the appropriate interrupt handler routine to handle the I/O operation.
d) A clock interrupt:
- A clock interrupt is a specific type of hardware interrupt generated by the system clock or a timer device.
- It is used to keep track of time and schedule tasks.
- The clock interrupt occurs at regular intervals and is used by the operating system to perform various time-related operations, such as updating the system time, scheduling tasks, etc.
Conclusion:
In conclusion, a hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program. An external interrupt, also known as a hardware interrupt, is triggered by an external hardware device and is used for input/output operations. Therefore, the correct answer is option 'B' - Also called an external interrupt.
Given below are some statements associated with cache memory. Identify the correct statement.- a)The Level 1 cache is always faster than the Level 2 cache.
- b)The Level 2 cache is used to mitigate the dynamic slowdown every time a Level 1 cache miss occurs.
- c)Level 2 cache comes as on board only. .
- d)In modern day computers, the Level 2 cache is considered an internal cache.
Correct answer is option 'B'. Can you explain this answer?
Given below are some statements associated with cache memory. Identify the correct statement.
a)
The Level 1 cache is always faster than the Level 2 cache.
b)
The Level 2 cache is used to mitigate the dynamic slowdown every time a Level 1 cache miss occurs.
c)
Level 2 cache comes as on board only. .
d)
In modern day computers, the Level 2 cache is considered an internal cache.
|
|
Gauri Banerjee answered |
The level-1 cache may be of same speed as level- 2 the level-2 cache used to mitigate the dynamic slow down every time a level-1 cache miss occur level-1 cache comes on processor chip while level-2 cache comes on external chip.
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte- wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?- a)15
- b)25
- c)35
- d)45
Correct answer is option 'B'. Can you explain this answer?
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte- wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?
a)
15
b)
25
c)
35
d)
45
|
Sushant Nambiar answered |
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______- a)Generation word
- b)Exception handling
- c)Imprecise exceptions
- d)None of the mentioned
Correct answer is option 'C'. Can you explain this answer?
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______
a)
Generation word
b)
Exception handling
c)
Imprecise exceptions
d)
None of the mentioned
|
Ipsita Patel answered |
Imprecise exceptions
In computer programming, an exception is a condition that occurs during the execution of a program that disrupts the normal flow of instructions. When an exception is raised, it typically causes the program to terminate abruptly or to jump to an exception handler to handle the error. However, the behavior of the processor when an exception is raised and the succeeding instructions are executed completely can vary depending on the architecture and design of the processor.
Imprecise exceptions
When an exception is raised and the succeeding instructions are executed completely, it is referred to as imprecise exceptions. This means that the processor executes the instructions following the exception even though the exception has not been resolved or handled. This behavior can lead to incorrect or unpredictable results because the program continues to execute without properly handling the exception.
Impact of imprecise exceptions
Imprecise exceptions can have significant implications for the correctness and reliability of a program. When an exception occurs, it is typically important to handle the exception properly in order to ensure that the program continues to execute correctly. However, if the processor allows the program to continue executing without resolving the exception, it can result in incorrect computations, data corruption, or other unexpected behavior.
Handling exceptions
To ensure the proper handling of exceptions, it is important to design and implement exception handling mechanisms in the program. These mechanisms typically involve defining exception handlers that specify how to handle specific types of exceptions. When an exception occurs, the processor can then jump to the appropriate exception handler to handle the error and take the necessary actions.
Conclusion
In summary, when an exception is raised and the succeeding instructions are executed completely, the processor is said to have imprecise exceptions. This behavior can have significant implications for the correctness and reliability of a program, as it can lead to incorrect computations or unexpected behavior. Therefore, it is important to design and implement proper exception handling mechanisms to ensure that exceptions are handled appropriately and the program continues to execute correctly.
In computer programming, an exception is a condition that occurs during the execution of a program that disrupts the normal flow of instructions. When an exception is raised, it typically causes the program to terminate abruptly or to jump to an exception handler to handle the error. However, the behavior of the processor when an exception is raised and the succeeding instructions are executed completely can vary depending on the architecture and design of the processor.
Imprecise exceptions
When an exception is raised and the succeeding instructions are executed completely, it is referred to as imprecise exceptions. This means that the processor executes the instructions following the exception even though the exception has not been resolved or handled. This behavior can lead to incorrect or unpredictable results because the program continues to execute without properly handling the exception.
Impact of imprecise exceptions
Imprecise exceptions can have significant implications for the correctness and reliability of a program. When an exception occurs, it is typically important to handle the exception properly in order to ensure that the program continues to execute correctly. However, if the processor allows the program to continue executing without resolving the exception, it can result in incorrect computations, data corruption, or other unexpected behavior.
Handling exceptions
To ensure the proper handling of exceptions, it is important to design and implement exception handling mechanisms in the program. These mechanisms typically involve defining exception handlers that specify how to handle specific types of exceptions. When an exception occurs, the processor can then jump to the appropriate exception handler to handle the error and take the necessary actions.
Conclusion
In summary, when an exception is raised and the succeeding instructions are executed completely, the processor is said to have imprecise exceptions. This behavior can have significant implications for the correctness and reliability of a program, as it can lead to incorrect computations or unexpected behavior. Therefore, it is important to design and implement proper exception handling mechanisms to ensure that exceptions are handled appropriately and the program continues to execute correctly.
Consider the C struct defined below:
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using- a)Post-increment addressing mode, (R1)+
- b)Pre-decrement addressing mode, -(R1)
- c)Register direct addressing mode, R1
- d)Index addressing mode, X(R1), where X is an offset represented in 2's complement 16-bit representation.
Correct answer is option 'D'. Can you explain this answer?
Consider the C struct defined below:
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using
a)
Post-increment addressing mode, (R1)+
b)
Pre-decrement addressing mode, -(R1)
c)
Register direct addressing mode, R1
d)
Index addressing mode, X(R1), where X is an offset represented in 2's complement 16-bit representation.
|
|
Anagha Choudhary answered |
Option (D)
Displacement Mode :-
Similar to index mode, except instead of a index register a base register will be used. Base register contains a pointer to a memory location. An integer (constant) is also referred to as a displacement. The address of the operand is obtained by
adding the contents of the base register plus the constant. The difference between index mode and displacement mode is in the number of bits used to represent the constant. When the constant is represented a number of bits to access the
memory, then we have index mode. Index mode is more appropriate for array accessing; displacement mode is more appropriate for structure (records) accessing.
Similar to index mode, except instead of a index register a base register will be used. Base register contains a pointer to a memory location. An integer (constant) is also referred to as a displacement. The address of the operand is obtained by
adding the contents of the base register plus the constant. The difference between index mode and displacement mode is in the number of bits used to represent the constant. When the constant is represented a number of bits to access the
memory, then we have index mode. Index mode is more appropriate for array accessing; displacement mode is more appropriate for structure (records) accessing.
For interval arithmetic best rounding technique use is ________.- a)Rounding to plus and minus infinity
- b)Rounding to zero
- c)Rounding to nearest
- d)None of these
Correct answer is option 'A'. Can you explain this answer?
For interval arithmetic best rounding technique use is ________.
a)
Rounding to plus and minus infinity
b)
Rounding to zero
c)
Rounding to nearest
d)
None of these
|
Diya Chauhan answered |
Rounding to plus and minus infinity are useful in implementing a technique known as interval arithmetic. Interval arithmetic provides an efficient method for monitoring and controlling errors in floating point computations by producing two values for each result. The two values correspond to the lower and upper endpoints of an interval that contains the true result. The width of the interval, which is the difference between the upper and lower endpoints, indicates the accuracy of the result of the endpoints of an interval are not representable then the interval endpoints are rounded down and up respectively.
A system which has lot of crashes, data should be written to the disk using- a)Write-through
- b)Write-back
- c)Both of the above
- d)None of thes
Correct answer is option 'B'. Can you explain this answer?
A system which has lot of crashes, data should be written to the disk using
a)
Write-through
b)
Write-back
c)
Both of the above
d)
None of thes
|
Pallabi Sharma answered |
System should write data immediately So called it write-back.
System calls are usually invoked by using
1. An indirect jump
2. A software interrupt
3. Polling
4. A privileged instruction- a)2 and 3
- b)1 and 3
- c)1, 2, 3 and 4
- d)3 and 4
Correct answer is option 'A'. Can you explain this answer?
System calls are usually invoked by using
1. An indirect jump
2. A software interrupt
3. Polling
4. A privileged instruction
1. An indirect jump
2. A software interrupt
3. Polling
4. A privileged instruction
a)
2 and 3
b)
1 and 3
c)
1, 2, 3 and 4
d)
3 and 4
|
Harshitha Banerjee answered |
System call is a request in unit like operating system made via software interrupt by an active process for a service performed by the Kernal.
Consider a CPU has 8 general-purpose registers
R0, R1..., R7 and supports the following operations.
ADD Ra, Rb, Rc Add Ra to Rb and store the result to Rc.
MUL Ra, Rb, Rc Multiply Ra to Rb and store the result to Rc.
An operation normally takes one clock cycles, an operation takes two clock cycles if it produces a result required by the immediately following operations. Consider the expression XY + XYZ + YZ, where variables X, Y and Z are initially located in the registers R0, R1 and R2. If contents these registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of XY + XYZ + YZ?- a)4
- b)5
- c)6
- d)7
Correct answer is option 'C'. Can you explain this answer?
Consider a CPU has 8 general-purpose registers
R0, R1..., R7 and supports the following operations.
ADD Ra, Rb, Rc Add Ra to Rb and store the result to Rc.
MUL Ra, Rb, Rc Multiply Ra to Rb and store the result to Rc.
An operation normally takes one clock cycles, an operation takes two clock cycles if it produces a result required by the immediately following operations. Consider the expression XY + XYZ + YZ, where variables X, Y and Z are initially located in the registers R0, R1 and R2. If contents these registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of XY + XYZ + YZ?
R0, R1..., R7 and supports the following operations.
ADD Ra, Rb, Rc Add Ra to Rb and store the result to Rc.
MUL Ra, Rb, Rc Multiply Ra to Rb and store the result to Rc.
An operation normally takes one clock cycles, an operation takes two clock cycles if it produces a result required by the immediately following operations. Consider the expression XY + XYZ + YZ, where variables X, Y and Z are initially located in the registers R0, R1 and R2. If contents these registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of XY + XYZ + YZ?
a)
4
b)
5
c)
6
d)
7
|
Jatin Joshi answered |
The immediate addressing modes can be used for ______
1. Loading internal registers with initial value.
2. Perform arithmetic or logical operation on immediate data.- a) Only 1
- b)Only 2
- c) Either 1 or 2
- d)Neither 1 nor 2
Correct answer is option 'C'. Can you explain this answer?
The immediate addressing modes can be used for ______
1. Loading internal registers with initial value.
2. Perform arithmetic or logical operation on immediate data.
1. Loading internal registers with initial value.
2. Perform arithmetic or logical operation on immediate data.
a)
Only 1
b)
Only 2
c)
Either 1 or 2
d)
Neither 1 nor 2
|
|
Sagar Dasgupta answered |
Immediate addressing modes can be used for either loading internal register with initial value or perform arithmetic or logical operation on immediate data.
Consider a high-level language statement while [* i - -] then which addressing mode is suitable for it?- a)Autoincrement
- b)Indexed
- c)Displacement
- d)Autodecrement
Correct answer is option 'D'. Can you explain this answer?
Consider a high-level language statement while [* i - -] then which addressing mode is suitable for it?
a)
Autoincrement
b)
Indexed
c)
Displacement
d)
Autodecrement
|
Pranav Patel answered |
In given while loop i is a pointer variable so autodecrement addressing mode is suitable.
A CPU has a cache with block size 64 bytes. The main memory has k blocks, each block being c bytes wide. Consecutive c-byte chunks are mapped on consecutive blocks with warp-around. All the k blocks can be accessed in parallel, but two accesses to the same block must be serialized. A cache block access may involve multiple iterations of parallel block accesses depending on the amount of data obtained by accessing all the k-blocks in parallel. Each iteration requires decoding the block numbers to be accessed in parallel and this takes k/2 ns.
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is- a)92 ns
- b)104 ns
- c)172 ns
- d)184 ns
Correct answer is option 'D'. Can you explain this answer?
A CPU has a cache with block size 64 bytes. The main memory has k blocks, each block being c bytes wide. Consecutive c-byte chunks are mapped on consecutive blocks with warp-around. All the k blocks can be accessed in parallel, but two accesses to the same block must be serialized. A cache block access may involve multiple iterations of parallel block accesses depending on the amount of data obtained by accessing all the k-blocks in parallel. Each iteration requires decoding the block numbers to be accessed in parallel and this takes k/2 ns.
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is
a)
92 ns
b)
104 ns
c)
172 ns
d)
184 ns
|
|
Kajal Sharma answered |
Cache block size = 64 bytes
Main memory has K banks or k = 24
Each bank is 2 byte long because c = 2
Total time for one parallel access
Total latency time = CT
= 2 x 92 = 184 ns
Main memory has K banks or k = 24
Each bank is 2 byte long because c = 2
Total time for one parallel access
Total latency time = CT
= 2 x 92 = 184 ns
What is computer architecture?- a)set of categories and methods that specify the functioning, organisation, and implementation of computer systems
- b)set of principles and methods that specify the functioning, organisation, and implementation of computer systems
- c)set of functions and methods that specify the functioning, organisation, and implementation of computer systems
- d)None of the mentioned
Correct answer is option 'B'. Can you explain this answer?
What is computer architecture?
a)
set of categories and methods that specify the functioning, organisation, and implementation of computer systems
b)
set of principles and methods that specify the functioning, organisation, and implementation of computer systems
c)
set of functions and methods that specify the functioning, organisation, and implementation of computer systems
d)
None of the mentioned
|
Rohan Patel answered |
Computer architecture refers to the set of principles and methods that specify the functioning, organization, and implementation of computer systems. It encompasses the structure, behavior, and design of computers, including the hardware components and the software systems that control and coordinate their operation.
Key Points:
- Set of principles and methods: Computer architecture defines the fundamental principles and techniques for designing and implementing computer systems. It provides a framework for understanding how different components of a computer system interact and work together.
- Functioning: Computer architecture determines how the various components of a computer system, such as the CPU, memory, and input/output devices, function and interact with each other. It specifies the operations and functionalities that can be performed by the system.
- Organization: Computer architecture involves the organization and arrangement of the components within a computer system. It defines the structure and hierarchy of the various hardware components and their connections, as well as the organization of data and instructions in memory.
- Implementation: Computer architecture also deals with the implementation of computer systems, including the design and construction of the hardware components and the development of the software systems that run on them. It encompasses both the physical aspects of computer systems, such as the circuits and chips, as well as the software layers that enable their operation.
Importance of Computer Architecture:
- Performance: Computer architecture plays a crucial role in determining the performance of a computer system. By optimizing the design and organization of the components, it can enhance the speed and efficiency of computations and data processing.
- Scalability: Computer architecture also enables the scalability of computer systems, allowing them to handle larger workloads and accommodate future technological advancements. It provides a foundation for building systems that can be easily upgraded and expanded.
- Compatibility: Computer architecture ensures compatibility between different hardware and software components, allowing them to work together seamlessly. It defines standard interfaces and protocols that enable interoperability and easy integration of various system components.
- Reliability: A well-designed computer architecture enhances the reliability and fault tolerance of a system. By incorporating redundancy and error detection mechanisms, it can prevent and recover from hardware and software failures.
- Power Efficiency: Computer architecture also considers power efficiency and energy consumption. It aims to minimize power usage while maintaining optimal performance, especially in mobile and embedded systems.
In conclusion, computer architecture is a set of principles and methods that define the functioning, organization, and implementation of computer systems. It provides the foundation for designing and building efficient, scalable, and reliable computer systems.
Key Points:
- Set of principles and methods: Computer architecture defines the fundamental principles and techniques for designing and implementing computer systems. It provides a framework for understanding how different components of a computer system interact and work together.
- Functioning: Computer architecture determines how the various components of a computer system, such as the CPU, memory, and input/output devices, function and interact with each other. It specifies the operations and functionalities that can be performed by the system.
- Organization: Computer architecture involves the organization and arrangement of the components within a computer system. It defines the structure and hierarchy of the various hardware components and their connections, as well as the organization of data and instructions in memory.
- Implementation: Computer architecture also deals with the implementation of computer systems, including the design and construction of the hardware components and the development of the software systems that run on them. It encompasses both the physical aspects of computer systems, such as the circuits and chips, as well as the software layers that enable their operation.
Importance of Computer Architecture:
- Performance: Computer architecture plays a crucial role in determining the performance of a computer system. By optimizing the design and organization of the components, it can enhance the speed and efficiency of computations and data processing.
- Scalability: Computer architecture also enables the scalability of computer systems, allowing them to handle larger workloads and accommodate future technological advancements. It provides a foundation for building systems that can be easily upgraded and expanded.
- Compatibility: Computer architecture ensures compatibility between different hardware and software components, allowing them to work together seamlessly. It defines standard interfaces and protocols that enable interoperability and easy integration of various system components.
- Reliability: A well-designed computer architecture enhances the reliability and fault tolerance of a system. By incorporating redundancy and error detection mechanisms, it can prevent and recover from hardware and software failures.
- Power Efficiency: Computer architecture also considers power efficiency and energy consumption. It aims to minimize power usage while maintaining optimal performance, especially in mobile and embedded systems.
In conclusion, computer architecture is a set of principles and methods that define the functioning, organization, and implementation of computer systems. It provides the foundation for designing and building efficient, scalable, and reliable computer systems.
The CPU initializes the DMA by sending ______ .- a)The starting address of the memory blocks where data is available or where data is to be stored.
- b)The word count.
- c)Control for mode and start the transfer.
- d)All of these
Correct answer is option 'D'. Can you explain this answer?
The CPU initializes the DMA by sending ______ .
a)
The starting address of the memory blocks where data is available or where data is to be stored.
b)
The word count.
c)
Control for mode and start the transfer.
d)
All of these
|
|
Soumya Dey answered |
The CPU initializes the DMA by sending:
The starting address of the memory blocks where data are available (for read) or where data are to be stored. (For write)
The word count, which is the number of words in the memory.
Control to specify the mode of transfer such as read or write.
The starting address of the memory blocks where data are available (for read) or where data are to be stored. (For write)
The word count, which is the number of words in the memory.
Control to specify the mode of transfer such as read or write.
An 8-Bit DMA Device is operating'is Cycle Stealing Mode (Single Transfer Mode). Each DMA cycle is of 6 clock states and DMA clock is 2 MHz. Intermediate CPU machine cycle takes 2 μsa, determine the DMA Data Transfer Rat- a)100 Kbytes/sec
- b)200 Kbytes/sec
- c)350 Kbytes/sec
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
An 8-Bit DMA Device is operating'is Cycle Stealing Mode (Single Transfer Mode). Each DMA cycle is of 6 clock states and DMA clock is 2 MHz. Intermediate CPU machine cycle takes 2 μsa, determine the DMA Data Transfer Rat
a)
100 Kbytes/sec
b)
200 Kbytes/sec
c)
350 Kbytes/sec
d)
None of these
|
|
Nilesh Chavan answered |
DMA Clock is 2 MHz ⇒ Each DMA Clock state is 0.5μs
Each DMA Cycle has 6 Clock States ⇒ Each DMA cycle is of 3 μs
In Cycle Stealing 1 CPU and 1 DMA Cycles run alternately and the CPU Cycle takes 2 μs.
Therefore, every 3 + 2 = 5 μs, 1 byte is transferred by DMA device.
Data Transfer Rate = 1000000/5 x 1 Byte
= 200 Kbytes / Sec
Each DMA Cycle has 6 Clock States ⇒ Each DMA cycle is of 3 μs
In Cycle Stealing 1 CPU and 1 DMA Cycles run alternately and the CPU Cycle takes 2 μs.
Therefore, every 3 + 2 = 5 μs, 1 byte is transferred by DMA device.
Data Transfer Rate = 1000000/5 x 1 Byte
= 200 Kbytes / Sec
______ is a piece of hardware that executes a set of machine-language instructions.- a)Controller
- b)Bus
- c)Processor
- d)Motherboard
Correct answer is option 'C'. Can you explain this answer?
______ is a piece of hardware that executes a set of machine-language instructions.
a)
Controller
b)
Bus
c)
Processor
d)
Motherboard
|
Ipsita Dasgupta answered |
Processor or processing unit is an electronic CKT which perform operations on some external source, usually memory or some data stream. Processor executes a set of machine language instructions.
Cache memory- a)Has greater capacity than RAM
- b)Is faster to access than CPU registers
- c)Is permanent storage
- d)Faster to access than RAM.
Correct answer is option 'D'. Can you explain this answer?
Cache memory
a)
Has greater capacity than RAM
b)
Is faster to access than CPU registers
c)
Is permanent storage
d)
Faster to access than RAM.
|
Lekshmi Shah answered |
Cache memory is faster to access than RAM but slower to access than CPU register.
Suppose a CPU contains 1000 memory references there are 40 misses in L1 cache (First Level Cache) and 20 misses in the L2 cache (Second Level Cache). Assume miss penalty from the L2 cache to memory is 100 clock cycles the hit time of L2 cache is 10 clock cycles, the hit time of L1 cache is 1 clock cycle and "there are 1.5 memory references per instruction.Q. What is the average memory access time?- a)3.4 clock cycles
- b)3.5 clock cycles
- c)5.3 clock cycles
- d)1.8 clock cycles
Correct answer is option 'A'. Can you explain this answer?
Suppose a CPU contains 1000 memory references there are 40 misses in L1 cache (First Level Cache) and 20 misses in the L2 cache (Second Level Cache). Assume miss penalty from the L2 cache to memory is 100 clock cycles the hit time of L2 cache is 10 clock cycles, the hit time of L1 cache is 1 clock cycle and "there are 1.5 memory references per instruction.
Q. What is the average memory access time?
a)
3.4 clock cycles
b)
3.5 clock cycles
c)
5.3 clock cycles
d)
1.8 clock cycles
|
|
Gargi Menon answered |
Which of the following statements is false about CISC architectures?- a)CISC machine instructions may include complex addressing modes, which require many clock cycles to carry out.
- b)CISC control units are typically microprogrammed, allowing the instruction set to be more flexible.
- c)In the CISC instruction set, all arithmetic/logic instructions must be register based.
- d)CISC architectures may perform better in network centric applications than RISC.
Correct answer is option 'C'. Can you explain this answer?
Which of the following statements is false about CISC architectures?
a)
CISC machine instructions may include complex addressing modes, which require many clock cycles to carry out.
b)
CISC control units are typically microprogrammed, allowing the instruction set to be more flexible.
c)
In the CISC instruction set, all arithmetic/logic instructions must be register based.
d)
CISC architectures may perform better in network centric applications than RISC.
|
Vikram Bansal answered |
In RISC instruction set all arithmetic/logic instructions must be register-based but not in CISC.
The 2’s complement representation of the decimal value - 15 is- a)1111
- b)11111
- c)111111
- d)10001
Correct answer is option 'D'. Can you explain this answer?
The 2’s complement representation of the decimal value - 15 is
a)
1111
b)
11111
c)
111111
d)
10001
|
Pranab Banerjee answered |
The 2’s complement of negative numbers are represented as the binary number that when added to a positive number of the same magnitude equals zero
+15 = 0 1 1 1 1
The 2’s complement representation of the decimal value -15 is
-15 in 2’s complement = 10001
+15 = 0 1 1 1 1
The 2’s complement representation of the decimal value -15 is
-15 in 2’s complement = 10001
A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a throughput of- a)1/3
- b)1/7
- c)7
- d)3
Correct answer is option 'A'. Can you explain this answer?
A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a throughput of
a)
1/3
b)
1/7
c)
7
d)
3
|
|
Akshay Singh answered |
First output will come after 5 time units, then after every 3 time units, we will get the output. So throughput 1/3.
Given a 5 stage pipeline with stages taking 1,2, 3, 1, 1 units of time, the clock period of the pipeline is- a)8
- b)1/8
- c)1/3
- d)3
Correct answer is option 'D'. Can you explain this answer?
Given a 5 stage pipeline with stages taking 1,2, 3, 1, 1 units of time, the clock period of the pipeline is
a)
8
b)
1/8
c)
1/3
d)
3
|
Rohit Mukherjee answered |
Clock period of pipeline = Maximum delay of stages
= Max ( 1, 2, 3, 1, 1) = 3
= Max ( 1, 2, 3, 1, 1) = 3
________ are the different type/s of generating control signals.- a)Hardwired
- b)Micro-instruction
- c)Micro-programmed
- d)Both Micro-programmed and Hardwired
Correct answer is option 'D'. Can you explain this answer?
________ are the different type/s of generating control signals.
a)
Hardwired
b)
Micro-instruction
c)
Micro-programmed
d)
Both Micro-programmed and Hardwired
|
Amar Majumdar answered |
Generating Control Signals
There are different types of generating control signals, which are as follows:
1. Hardwired Control Signals:
Hardwired control signals are generated by using the combinational logic circuits. These circuits are designed using logic gates, such as AND, OR, NOT gates, etc. The control signals generated by these circuits are directly applied to the control unit.
2. Micro-instruction Control Signals:
Micro-instruction control signals are generated by using micro-instructions. These micro-instructions are stored in the control memory. The control unit reads these micro-instructions and generates the control signals accordingly.
3. Micro-programmed Control Signals:
Micro-programmed control signals are generated by using micro-programs. Micro-programs are stored in the control memory. These programs are written in machine language and are executed by the control unit. The control unit reads these programs and generates the control signals accordingly.
Both Micro-programmed and Hardwired:
Both micro-programmed and hardwired control signals are used in modern computing systems. Some control signals are generated by using combinational logic circuits, while others are generated by using micro-instructions or micro-programs.
Conclusion:
In conclusion, generating control signals is an important aspect of computer architecture. The choice of control signal generation method depends on the specific requirements of the system. Hardwired, micro-instruction, and micro-programmed control signals are the different types of generating control signals.
There are different types of generating control signals, which are as follows:
1. Hardwired Control Signals:
Hardwired control signals are generated by using the combinational logic circuits. These circuits are designed using logic gates, such as AND, OR, NOT gates, etc. The control signals generated by these circuits are directly applied to the control unit.
2. Micro-instruction Control Signals:
Micro-instruction control signals are generated by using micro-instructions. These micro-instructions are stored in the control memory. The control unit reads these micro-instructions and generates the control signals accordingly.
3. Micro-programmed Control Signals:
Micro-programmed control signals are generated by using micro-programs. Micro-programs are stored in the control memory. These programs are written in machine language and are executed by the control unit. The control unit reads these programs and generates the control signals accordingly.
Both Micro-programmed and Hardwired:
Both micro-programmed and hardwired control signals are used in modern computing systems. Some control signals are generated by using combinational logic circuits, while others are generated by using micro-instructions or micro-programs.
Conclusion:
In conclusion, generating control signals is an important aspect of computer architecture. The choice of control signal generation method depends on the specific requirements of the system. Hardwired, micro-instruction, and micro-programmed control signals are the different types of generating control signals.
Which of the following is the subcategories of computer architecture?
- a)All of the mentioned
- b)Instruction set architecture
- c)Systems design
- d)Microarchitecture
Correct answer is option 'A'. Can you explain this answer?
Which of the following is the subcategories of computer architecture?
a)
All of the mentioned
b)
Instruction set architecture
c)
Systems design
d)
Microarchitecture
|
|
Rohan Patel answered |
Introduction:
Computer architecture refers to the design and organization of the various components (hardware and software) in a computer system. It encompasses the structure, behavior, and functionality of a computer system. There are several subcategories of computer architecture that focus on different aspects of the design and implementation of a computer system.
Microarchitecture:
Microarchitecture, also known as computer organization, is a subcategory of computer architecture that deals with the internal structure and design of a computer processor. It focuses on how the processor implements the instructions specified by the instruction set architecture. Microarchitecture includes components such as the control unit, arithmetic logic unit, memory hierarchy, and data paths.
Instruction Set Architecture:
Instruction Set Architecture (ISA) is another subcategory of computer architecture. It defines the set of instructions that a computer can understand and execute. It specifies the operations that can be performed, the data types supported, the addressing modes, and the format of instructions. The ISA acts as an interface between the hardware and software layers of a computer system.
Systems Design:
Systems design is a broader subcategory of computer architecture that encompasses the overall design and organization of a computer system. It includes considerations such as the selection of hardware components, the design of the memory hierarchy, the interconnection of components, and the configuration of the system. Systems design takes into account factors such as performance, reliability, scalability, and cost.
Conclusion:
In summary, microarchitecture, instruction set architecture, and systems design are all subcategories of computer architecture. Microarchitecture focuses on the internal structure of a computer processor, instruction set architecture defines the instructions that a computer can understand, and systems design encompasses the overall design and organization of a computer system.
Computer architecture refers to the design and organization of the various components (hardware and software) in a computer system. It encompasses the structure, behavior, and functionality of a computer system. There are several subcategories of computer architecture that focus on different aspects of the design and implementation of a computer system.
Microarchitecture:
Microarchitecture, also known as computer organization, is a subcategory of computer architecture that deals with the internal structure and design of a computer processor. It focuses on how the processor implements the instructions specified by the instruction set architecture. Microarchitecture includes components such as the control unit, arithmetic logic unit, memory hierarchy, and data paths.
Instruction Set Architecture:
Instruction Set Architecture (ISA) is another subcategory of computer architecture. It defines the set of instructions that a computer can understand and execute. It specifies the operations that can be performed, the data types supported, the addressing modes, and the format of instructions. The ISA acts as an interface between the hardware and software layers of a computer system.
Systems Design:
Systems design is a broader subcategory of computer architecture that encompasses the overall design and organization of a computer system. It includes considerations such as the selection of hardware components, the design of the memory hierarchy, the interconnection of components, and the configuration of the system. Systems design takes into account factors such as performance, reliability, scalability, and cost.
Conclusion:
In summary, microarchitecture, instruction set architecture, and systems design are all subcategories of computer architecture. Microarchitecture focuses on the internal structure of a computer processor, instruction set architecture defines the instructions that a computer can understand, and systems design encompasses the overall design and organization of a computer system.
A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called _______ .- a)I/O processor
- b)DMA controller
- c)Data communication processor
- d)USART
Correct answer is option 'D'. Can you explain this answer?
A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called _______ .
a)
I/O processor
b)
DMA controller
c)
Data communication processor
d)
USART
|
Sanmit Vartak answered |
Data communication processor is the processor that communicate with remote terminals over telephone and other communication media in a serial fashion.
To prevent signals, from colliding on the bus, _______ prioritize access to memory by I/O channels and processors.- a)A register
- b)Interrupts '
- c)The processor scheduler
- d)A controller
Correct answer is option 'D'. Can you explain this answer?
To prevent signals, from colliding on the bus, _______ prioritize access to memory by I/O channels and processors.
a)
A register
b)
Interrupts '
c)
The processor scheduler
d)
A controller
|
Megha Dasgupta answered |
To prevent signals from colliding on the bus, a controller prioritize access to memory by I/O channels and processors.
The disadvantage of hard-wired control units with flip-flops is ______.- a)Design becomes complex
- b)It require more number of flip-flops
- c)Control circuit speed does not matches with flip-flops
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
The disadvantage of hard-wired control units with flip-flops is ______.
a)
Design becomes complex
b)
It require more number of flip-flops
c)
Control circuit speed does not matches with flip-flops
d)
None of these
|
Meghana Rane answered |
The disadvantage of hardwired control units with flip-flops is that it requires more number of flip- flops.
Which of the following control signals has separate destinations?- a)Data Paths
- b)ALU & System Bus
- c)Data Paths, ALU & System Bus
- d)None of the above
Correct answer is option 'A'. Can you explain this answer?
Which of the following control signals has separate destinations?
a)
Data Paths
b)
ALU & System Bus
c)
Data Paths, ALU & System Bus
d)
None of the above
|
|
Sudhir Patel answered |
The data path is the collection of functional units such as arithmetic logic units or multipliers. The data path is required to perform data processing operations.
Typically, in a microprocessor, the units in at least one of the datapaths would be: instruction registers, decode latch, ALU registers, load-store unit, writeback unit, and the memory.
To perform any operation in the CPU, data follows a specific path within the CPU to execute the instruction.
Typically, in a microprocessor, the units in at least one of the datapaths would be: instruction registers, decode latch, ALU registers, load-store unit, writeback unit, and the memory.
To perform any operation in the CPU, data follows a specific path within the CPU to execute the instruction.
Which of the following is not valid class of interrupts?
1. Program
2. Timer
3. I/O
4. Hardware failure- a)1 and 3
- b)1, 2 and 4
- c)2 and 3
- d)None of these
Correct answer is option 'D'. Can you explain this answer?
Which of the following is not valid class of interrupts?
1. Program
2. Timer
3. I/O
4. Hardware failure
1. Program
2. Timer
3. I/O
4. Hardware failure
a)
1 and 3
b)
1, 2 and 4
c)
2 and 3
d)
None of these
|
|
Milan Mukherjee answered |
1, 2, 3, 4 are valid classes of interrupts:
1. Program: generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero etc.
2. Timer: generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.
3. I/O: generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error condition.
4. Hardware failure: generated by failure such as power failure or memories parity error.
1. Program: generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero etc.
2. Timer: generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.
3. I/O: generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error condition.
4. Hardware failure: generated by failure such as power failure or memories parity error.
The register which holds the address of the location to or from which data are to be transferred is known as- a)Index register
- b)Instruction register
- c)Memory address register
- d)Memory data register
Correct answer is option 'C'. Can you explain this answer?
The register which holds the address of the location to or from which data are to be transferred is known as
a)
Index register
b)
Instruction register
c)
Memory address register
d)
Memory data register
|
|
Harshad Mukherjee answered |
MAR is a register that holds the address of location to or from which data are to be transferred.
Which of the following affects processing power?- a)Data bus capacity
- b)Addressing scheme
- c)Clockspeed
- d)All of these
Correct answer is option 'D'. Can you explain this answer?
Which of the following affects processing power?
a)
Data bus capacity
b)
Addressing scheme
c)
Clockspeed
d)
All of these
|
|
Ameya Basak answered |
Processing power depends on clock speed, data bus capacity and addressing scheme.
The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is
executed.
MOVI Rs, 1 ; Move immediate
LOAD Rd, 1000 (Rs) ; Load from memory
ADDI Rd, 1000 ; Add immediate
STOREI 0 (Rd), 20 ; Store immediate
Which of the statements below is TRUE after the program is executed ?- a)Memory location 1000 has value 20
- b)Memory location 1020 has value 20
- c)Memory location 1021 has value 20
- d)Memory location 1001 has value 20
Correct answer is option 'D'. Can you explain this answer?
The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is
executed.
MOVI Rs, 1 ; Move immediate
LOAD Rd, 1000 (Rs) ; Load from memory
ADDI Rd, 1000 ; Add immediate
STOREI 0 (Rd), 20 ; Store immediate
Which of the statements below is TRUE after the program is executed ?
executed.
MOVI Rs, 1 ; Move immediate
LOAD Rd, 1000 (Rs) ; Load from memory
ADDI Rd, 1000 ; Add immediate
STOREI 0 (Rd), 20 ; Store immediate
Which of the statements below is TRUE after the program is executed ?
a)
Memory location 1000 has value 20
b)
Memory location 1020 has value 20
c)
Memory location 1021 has value 20
d)
Memory location 1001 has value 20
|
|
Shivam Dasgupta answered |
D) Memory location 1001 has value 20.
Rs
1 (Immediate Addressing)
Rd 1 (Indexed Addressing, value at memory location 1+1000 = 1001 is loaded to Rd which is 1)
( Rd becomes 1+1000)
store in address 1001 20
Rs
1 (Immediate Addressing)Rd
1 (Indexed Addressing, value at memory location 1+1000 = 1001 is loaded to Rd which is 1)( Rd becomes 1+1000)
store in address 1001
20In caching system, the memory reference made in any short time interval tend to use only a small fraction of the total memory is called ______ .- a)Checkerboarding
- b)Locality principle
- c)Memory interleaving
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
In caching system, the memory reference made in any short time interval tend to use only a small fraction of the total memory is called ______ .
a)
Checkerboarding
b)
Locality principle
c)
Memory interleaving
d)
None of these
|
Malavika Banerjee answered |
It is the definition of locality principle.
We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions?- a)214 nsec
- b)202 nsec
- c)86 nsec
- d)200 nsec
Correct answer is option 'B'. Can you explain this answer?
We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions?
a)
214 nsec
b)
202 nsec
c)
86 nsec
d)
200 nsec
|
|
Anisha Ahuja answered |
Execution time for Pipeline
= (K + n - 1) x execution _time
Where, k = Number of stages in pipeline
n = Number of instructions execution time
= Max (all stages execution time)
D1 - (5 + 100 - 1 ) x 4 = 416
D2 = (8 + 100 - 1) x 2 = 214
Time saved using: D2 = 416 - 214 = 202
= (K + n - 1) x execution _time
Where, k = Number of stages in pipeline
n = Number of instructions execution time
= Max (all stages execution time)
D1 - (5 + 100 - 1 ) x 4 = 416
D2 = (8 + 100 - 1) x 2 = 214
Time saved using: D2 = 416 - 214 = 202
P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)16. The 2's complement representation of 8*P is- a)(C3D8)16
- b)(187B)16
- c)(F878)16
- d)(987B)16
Correct answer is option 'A'. Can you explain this answer?
P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)16. The 2's complement representation of 8*P is
a)
(C3D8)16
b)
(187B)16
c)
(F878)16
d)
(987B)16
|
|
Subhankar Goyal answered |
2’s complement of P is given as (F87B)16
2’s complement of 8 x P = 23 x (F87B)16
2’s complement of 8 x P = 23 x (F87B)16
Consider the unpipelined machine with 10 ns clock cycles. It uses four cycles for ALU operations and branches, whereas five cycles for memory operations. Assume that the relative frequencies of there operations are 40%, 20%, 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 ns overhead to the clock. How much speed up in the instruction execution rate will we gain from a pipeline?
- a)5 times
- b)4 times
- c)8 times
- d)4.5 times
Correct answer is option 'B'. Can you explain this answer?
Consider the unpipelined machine with 10 ns clock cycles. It uses four cycles for ALU operations and branches, whereas five cycles for memory operations. Assume that the relative frequencies of there operations are 40%, 20%, 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 ns overhead to the clock. How much speed up in the instruction execution rate will we gain from a pipeline?
a)
5 times
b)
4 times
c)
8 times
d)
4.5 times
|
|
Subham Saha answered |
Total clock cycle
Under non pipeline time = 4.4 x (10) = 44
Under pipeline time
= 10 + overhead = 10 + 1 = 11
So, speedup = 44/11 = 4 times
Which of the following holds data and processing instructions temporarily until the CPU needs it?- a)ROM
- b)Control unit
- c)Main memory
- d)Coprocessor chips
Correct answer is option 'C'. Can you explain this answer?
Which of the following holds data and processing instructions temporarily until the CPU needs it?
a)
ROM
b)
Control unit
c)
Main memory
d)
Coprocessor chips
|
|
Arpita Mehta answered |
All the data and instruction before start executing presents in main memory temporarily.
Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows 5 ns, 8 ns, 6 ns, 10 ns, 15 ns, 12 ns, 6 ns, 8 ns. Assume that pipe lining adds 1 ns of overhead. Find the speedup versus the single cycle data path.- a)4.67
- b)4.375
- c)4.44
- d)4.285
Correct answer is option 'B'. Can you explain this answer?
Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows 5 ns, 8 ns, 6 ns, 10 ns, 15 ns, 12 ns, 6 ns, 8 ns. Assume that pipe lining adds 1 ns of overhead. Find the speedup versus the single cycle data path.
a)
4.67
b)
4.375
c)
4.44
d)
4.285
|
|
Avantika Yadav answered |
Since the unpipelined machine executes all instructions in a single clock cycle, its average time per instruction is simply clock time. The dock is equal to the sum of the times for each step in the execution.
∴ Average instructions execution time
= 5 + 8 + 6 + 1 0 + 15 + 12 + 6 + 8
= 70
The dock cycle time on the pipelined machine must be the largest time for any stage in the pipeline (15 ns) + the overhead of 1 ns for a total of 16 ns.
∴ Speed from pipelining
∴ Average instructions execution time
= 5 + 8 + 6 + 1 0 + 15 + 12 + 6 + 8
= 70
The dock cycle time on the pipelined machine must be the largest time for any stage in the pipeline (15 ns) + the overhead of 1 ns for a total of 16 ns.
∴ Speed from pipelining
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