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What will be the fundamental frequency for the following circuit if each inverter delay is 100 nsec?
- a)1 GHz
- b)0.5 GHz
- c)3.34 MHz
- d)1.67 MHz
Correct answer is option 'D'. Can you explain this answer?
What will be the fundamental frequency for the following circuit if each inverter delay is 100 nsec?
a)
1 GHz
b)
0.5 GHz
c)
3.34 MHz
d)
1.67 MHz
|
Riverdale Learning Institute answered |
Given,
n = 3 as there are three gates with feedback
Tpd = 100 nsec
T = 2 × 3 × 10-7
T= 6 × 10-7
Fundamental Frequency is given by f
T = 2 × 3 × 10-7
T= 6 × 10-7
Fundamental Frequency is given by f
The symbol for two - input OR- gate in negative logic is:- a)
- b)
- c)
- d)
Correct answer is option 'C'. Can you explain this answer?
The symbol for two - input OR- gate in negative logic is:
a)
b)
c)
d)
|
|
Riverdale Learning Institute answered |
Let's assume two inputs be A and B.
and the output is Y.
Using De-Morgan's Law:
Symbols of various logic gates:
1.) OR Gate:
2.) AND Gate:
3.) NOT Gate:
4.) NOR Gate:
5.) NAND Gate:
6.) XOR Gate:
7.) XNOR Gate:
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is- a)4
- b)5
- c)6
- d)7
Correct answer is option 'A'. Can you explain this answer?
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
a)
4
b)
5
c)
6
d)
7
|
Mohit Unni answered |
Explanation:
To implement a 2-input XOR gate using 2-input NAND gates, we can use the following logic:
1. Connect the two inputs A and B to two separate NAND gates (N1 and N2).
2. Connect the output of N1 to one input of another NAND gate (N3).
3. Connect the output of N2 to the other input of N3.
4. Connect the output of N3 to the input of another NAND gate (N4).
5. Connect the output of N1 to one input of another NAND gate (N5).
6. Connect the output of N2 to the other input of N5.
7. Connect the output of N4 and N5 to two separate inputs of another NAND gate (N6).
8. The output of N6 is the output of the XOR gate.
Calculation:
We can see that we need a total of 6 NAND gates (N1 to N6) to implement a 2-input XOR gate using 2-input NAND gates. Therefore, the correct answer is option A (4 is not enough and options B and C are too many).
Conclusion:
Thus, the minimum number of 2-input NAND gates required to implement a 2-input XOR gate is 6.
To implement a 2-input XOR gate using 2-input NAND gates, we can use the following logic:
1. Connect the two inputs A and B to two separate NAND gates (N1 and N2).
2. Connect the output of N1 to one input of another NAND gate (N3).
3. Connect the output of N2 to the other input of N3.
4. Connect the output of N3 to the input of another NAND gate (N4).
5. Connect the output of N1 to one input of another NAND gate (N5).
6. Connect the output of N2 to the other input of N5.
7. Connect the output of N4 and N5 to two separate inputs of another NAND gate (N6).
8. The output of N6 is the output of the XOR gate.
Calculation:
We can see that we need a total of 6 NAND gates (N1 to N6) to implement a 2-input XOR gate using 2-input NAND gates. Therefore, the correct answer is option A (4 is not enough and options B and C are too many).
Conclusion:
Thus, the minimum number of 2-input NAND gates required to implement a 2-input XOR gate is 6.
Examine these two statements carefully and select the answers to these items using the code given below:Statement (I): When all inputs of a NAND gate are shorted to get a single input, single output gate, it becomes an inverter.Statement (II): When all inputs of a NAND gate are at logic ‘0’ level, the output is at logic ‘0’ level.- a)Both Statement I and Statement II are individually true and Statement II is the correct explanation of Statement I
- b)Both Statement I and Statement II are individually true but Statement II is not the correct explanation of Statement I
- c)Statement I is true but Statement II is false
- d)Statement I is false but Statement II is true
Correct answer is option 'C'. Can you explain this answer?
Examine these two statements carefully and select the answers to these items using the code given below:
Statement (I): When all inputs of a NAND gate are shorted to get a single input, single output gate, it becomes an inverter.
Statement (II): When all inputs of a NAND gate are at logic ‘0’ level, the output is at logic ‘0’ level.
a)
Both Statement I and Statement II are individually true and Statement II is the correct explanation of Statement I
b)
Both Statement I and Statement II are individually true but Statement II is not the correct explanation of Statement I
c)
Statement I is true but Statement II is false
d)
Statement I is false but Statement II is true
|
Bayshore Academy answered |
______ is also known as Inverter.- a)NOT Gate
- b)OR Gate
- c)NAND Gate
- d)AND Gate
Correct answer is option 'A'. Can you explain this answer?
______ is also known as Inverter.
a)
NOT Gate
b)
OR Gate
c)
NAND Gate
d)
AND Gate
|
Ravi Singh answered |
- NOT Gate is also known as Inverter
- The 7404 is a high-speed CMOS Logic Quad NOT Gate.
- The 7404 is also known as Hex inverter.
- The contains Six independent NOT gates in one package. T
- The NOT gate consists of only one input and one output.
- A NOT gate is used to output the Boolean inverse of the applied input.
- Hence the name ‘Digital Inverter’ or ‘Inverting buffer’. The most commonly used NOT gate IC is 7404.
- The symbol and truth table of NOT gate and a buffer given as
The Boolean expression AB + AC̅ + BC simplifies to- a)BC + AC̅
- b)AB + AC̅ + B
- c)AB + AC̅
- d)AB + BC
Correct answer is option 'A'. Can you explain this answer?
The Boolean expression AB + AC̅ + BC simplifies to
a)
BC + AC̅
b)
AB + AC̅ + B
c)
AB + AC̅
d)
AB + BC
|
|
Ravi Singh answered |
Given Boolean expression is,
F = AB + AC̅ + BC
F = BC + AC̅
The output of logic circuit given below represents _______ gate.
- a)OR
- b)NOR
- c)AND
- d)NAND
Correct answer is option 'D'. Can you explain this answer?
The output of logic circuit given below represents _______ gate.
a)
OR
b)
NOR
c)
AND
d)
NAND
|
|
Riverdale Learning Institute answered |
Q= AB
Output expression Q is equivalent to NAND gate.
Output expression Q is equivalent to NAND gate.
How many AND and OR gates are required to realise Y = AB + BC + CD?- a)2,3
- b)2,2
- c)B and D
- d)3,1
Correct answer is option 'D'. Can you explain this answer?
How many AND and OR gates are required to realise Y = AB + BC + CD?
a)
2,3
b)
2,2
c)
B and D
d)
3,1
|
Talent Skill Learning answered |
To realise the expression Y = AB + BC + CD, follow these steps to determine the number of AND and OR gates required:
- Each product term (AB, BC, CD) needs an AND gate to combine the variables:
- AB needs 1 AND gate.
- BC needs 1 AND gate.
- CD needs 1 AND gate.
- An OR gate is used to sum the outputs of the AND gates:
- 1 OR gate for combining AB, BC, and CD.
Therefore, you need 3 AND gates and 1 OR gate.
Identify the logic gate shown in the figure?
- a)XNOR
- b)NAND
- c)NOR
- d)XOR
Correct answer is option 'C'. Can you explain this answer?
Identify the logic gate shown in the figure?
a)
XNOR
b)
NAND
c)
NOR
d)
XOR
|
|
Sanya Agarwal answered |
NOR GATE:
Symbol:
Truth Table:
Output equation:
Y=A+B
Output is high only when all inputs are low.
It is a universal gate
Y=A+B
Output is high only when all inputs are low.
It is a universal gate
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