Test: Counters - UPSC MCQ

From circuit we see 

T1=XQ1’+X’Q1—-(1) 

AND 

T2=(Q2 ? Q1)’—-(2) 

AND DESIRED OUTPUT IS 00->10->11->01->00 

SO X SHOULD BE Q1Q2’+Q1’Q2 SATISFYING 1 AND 2. 

SO ANS IS (D) PART. 

Initially A1 A2 A3 A4 =0000 

Clr=A1 and A3 

So when A1 and A3 both are 1 it again goes to 0000 

Hence 0000(init.) -> 0001(A1 and A3=0)->0010 (A1 and A3=0) -> 0011(A1 and A3=0) -> 0100 (A1 and A3=1)[ clear condition satisfied] ->0000(init.) so it goes through 0->1->2->3->4 

Ans is (C) part. 

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

A counter circuit is usually constructed of a number of flip-flops connected in cascade. Preferably, JK Flip-flops are used to construct counters and registers.

The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops is 0 to 2ⁿ-1. For say, there is a 2-bit counter, then it will count till 2²-1 = 3. Thus, it will count from 0 to 3.

Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter and such like.

Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as Decade Counter counting from 0 to 9.

Ripple counters are also called asynchronous counter. In Asynchronous counters, only the first flip-flop is connected to an external clock while the rest of the flip-flops have their preceding flip-flop output as clock to them.

Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.

The parallel outputs of a counter circuit represent the clock count. A counter counts the number of times an event takes place in accordance to the clock pulse.