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We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time Howmuch time can be saved using design D2 over design D1 for executing 100 instructions?
  • a)
    214 nsec
  • b)
    202 nsec
  • c)
    86 nsec
  • d)
    -200 nsec
Correct answer is option 'B'. Can you explain this answer?
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We have two designs D1 and D2 for a synchronous pipeline processor. D1...
(B) is the correct option for this question.
Execution time for Pipeline = (K+n-1)*execution_time where k = no of stages in pipeline n = no of instructions
execution time = Max(all stages execution time)
D1 = (5+100-1)*4 = 416
D2 = (8+100-1)*2 = 214
Time saved using D2 = 416-214 =202
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Most Upvoted Answer
We have two designs D1 and D2 for a synchronous pipeline processor. D1...
Time saved using Design D2 over Design D1:
Design D1:
- Number of pipeline stages: 5
- Execution times: 3nsec, 2nsec, 4nsec, 2nsec, 3nsec
Design D2:
- Number of pipeline stages: 8
- Execution time per stage: 2nsec

Calculating time taken by Design D1:
Total time taken by Design D1 = (5-1) * max(3, 2, 4, 2, 3) = 4 * 4 = 16 nsec per instruction

Calculating time taken by Design D2:
Total time taken by Design D2 = (8-1) * 2 = 14 nsec per instruction

Time saved by Design D2 over Design D1:
Time saved per instruction = 16 - 14 = 2 nsec
For 100 instructions = 100 * 2 = 200 nsec
Therefore, the time saved using Design D2 over Design D1 for executing 100 instructions is 200 nsec. Hence, the correct answer is option B) 202 nsec.
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We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time Howmuch time can be saved using design D2 over design D1 for executing 100 instructions?a)214 nsecb)202 nsecc)86 nsecd)-200 nsecCorrect answer is option 'B'. Can you explain this answer?
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We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time Howmuch time can be saved using design D2 over design D1 for executing 100 instructions?a)214 nsecb)202 nsecc)86 nsecd)-200 nsecCorrect answer is option 'B'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time Howmuch time can be saved using design D2 over design D1 for executing 100 instructions?a)214 nsecb)202 nsecc)86 nsecd)-200 nsecCorrect answer is option 'B'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time Howmuch time can be saved using design D2 over design D1 for executing 100 instructions?a)214 nsecb)202 nsecc)86 nsecd)-200 nsecCorrect answer is option 'B'. Can you explain this answer?.
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