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Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as
follows:
double ARR[1024][1024];
int i, j;
/*Initialize array ARR to 0.0 */
for(i = 0; i < 1024; i++)
for(j = 0; j < 1024; j++)
ARR[i][j] = 0.0;
The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in
row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the
program are those to array ARR.
The cache hit ratio for this initialization loop is
managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as
follows:
double ARR[1024][1024];
int i, j;
/*Initialize array ARR to 0.0 */
for(i = 0; i < 1024; i++)
for(j = 0; j < 1024; j++)
ARR[i][j] = 0.0;
The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in
row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the
program are those to array ARR.
The cache hit ratio for this initialization loop is
- a)0%
- b)25%
- c)50%
- d)75%
Correct answer is option 'C'. Can you explain this answer?
Verified Answer
Consider a machine with a 2-way set associative data cache of size 64 ...
block size=16B and one element=8B.so in one block 2 element will be stored.
for 1024*1024 element num of block required=1024*1024/2 =2^19 blocks required.
in one block first element will be a miss and second one is hit(since we are transferring two unit at a time)
=>hit ratio=total hit/total reference
=2^19/2^20
=1/2=0.5
=0.5*100=50%
for 1024*1024 element num of block required=1024*1024/2 =2^19 blocks required.
in one block first element will be a miss and second one is hit(since we are transferring two unit at a time)
=>hit ratio=total hit/total reference
=2^19/2^20
=1/2=0.5
=0.5*100=50%
This question is part of UPSC exam. View all Computer Science Engineering (CSE) courses
Most Upvoted Answer
Consider a machine with a 2-way set associative data cache of size 64 ...
Given Information:
- Cache size: 64 Kbytes
- Block size: 16 bytes
- Virtual address size: 32 bits
- Page size: 4 Kbytes
- Array size: 1024x1024
- Double size: 8 bytes
- Array starts at virtual page 0xFF000
Calculations:
1. Cache Blocks: The cache size is 64 Kbytes, and the block size is 16 bytes. Therefore, the cache is divided into (64 * 1024) / 16 = 4096 blocks.
2. Index Bits: Since the cache is 2-way set associative, each set contains 2 blocks. Therefore, the number of sets is 4096 / 2 = 2048. To address each set, we need log2(2048) = 11 bits for the index.
3. Offset Bits: The block size is 16 bytes, which requires log2(16) = 4 bits to address each byte within a block.
4. Tag Bits: The remaining bits of the virtual address after removing the index and offset bits are used for the tag. Therefore, tag bits = 32 - (11 + 4) = 17 bits.
5. Page Offset Bits: The page size is 4 Kbytes, which requires log2(4 * 1024) = 12 bits to address each byte within a page.
Explanation:
- The array ARR is stored in memory starting at the beginning of virtual page 0xFF000. Since the page size is 4 Kbytes, each page contains 4 * 1024 / 8 = 512 double elements.
- The initialization loop accesses all elements of ARR in row-major order. Therefore, the array elements are accessed sequentially.
- As the cache is initially empty, every memory reference will result in a cache miss. During the initialization loop, a total of 1024 * 1024 = 1048576 memory references will be made.
- Since the cache is 2-way set associative, each set contains 2 blocks. Therefore, the cache can store a maximum of 2 * 2048 = 4096 distinct memory blocks.
- As the loop progresses, the cache will fill up with the accessed memory blocks. Once the cache is full, any new memory reference will result in a cache miss and eviction of an existing block.
- Since the loop accesses all elements of ARR sequentially, each memory block will be evicted from the cache immediately after being accessed. Therefore, the cache hit ratio for this initialization loop is 0%.
- The cache hit ratio represents the percentage of memory references that result in a cache hit. In this case, all memory references result in cache misses, so the cache hit ratio is 0%.
Therefore, the correct answer is option 'A' - 0%.
- Cache size: 64 Kbytes
- Block size: 16 bytes
- Virtual address size: 32 bits
- Page size: 4 Kbytes
- Array size: 1024x1024
- Double size: 8 bytes
- Array starts at virtual page 0xFF000
Calculations:
1. Cache Blocks: The cache size is 64 Kbytes, and the block size is 16 bytes. Therefore, the cache is divided into (64 * 1024) / 16 = 4096 blocks.
2. Index Bits: Since the cache is 2-way set associative, each set contains 2 blocks. Therefore, the number of sets is 4096 / 2 = 2048. To address each set, we need log2(2048) = 11 bits for the index.
3. Offset Bits: The block size is 16 bytes, which requires log2(16) = 4 bits to address each byte within a block.
4. Tag Bits: The remaining bits of the virtual address after removing the index and offset bits are used for the tag. Therefore, tag bits = 32 - (11 + 4) = 17 bits.
5. Page Offset Bits: The page size is 4 Kbytes, which requires log2(4 * 1024) = 12 bits to address each byte within a page.
Explanation:
- The array ARR is stored in memory starting at the beginning of virtual page 0xFF000. Since the page size is 4 Kbytes, each page contains 4 * 1024 / 8 = 512 double elements.
- The initialization loop accesses all elements of ARR in row-major order. Therefore, the array elements are accessed sequentially.
- As the cache is initially empty, every memory reference will result in a cache miss. During the initialization loop, a total of 1024 * 1024 = 1048576 memory references will be made.
- Since the cache is 2-way set associative, each set contains 2 blocks. Therefore, the cache can store a maximum of 2 * 2048 = 4096 distinct memory blocks.
- As the loop progresses, the cache will fill up with the accessed memory blocks. Once the cache is full, any new memory reference will result in a cache miss and eviction of an existing block.
- Since the loop accesses all elements of ARR sequentially, each memory block will be evicted from the cache immediately after being accessed. Therefore, the cache hit ratio for this initialization loop is 0%.
- The cache hit ratio represents the percentage of memory references that result in a cache hit. In this case, all memory references result in cache misses, so the cache hit ratio is 0%.
Therefore, the correct answer is option 'A' - 0%.
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Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer?
Question Description
Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer?.
Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer?.
Solutions for Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE).
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Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer?, a detailed solution for Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? has been provided alongside types of Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? theory, EduRev gives you an
ample number of questions to practice Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache ismanaged using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins asfollows:double ARR[1024][1024];int i, j;/*Initialize array ARR to 0.0 */for(i = 0; i < 1024; i++)for(j = 0; j < 1024; j++)ARR[i][j] = 0.0;The size of double is 8 bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored inrow major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by theprogram are those to array ARR.The cache hit ratio for this initialization loop isa)0%b)25%c)50%d)75%Correct answer is option 'C'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
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