A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; iandlt;512; i++){for (j=0; jandlt;512; j++){x +=A[i] [j];}}P2:for (i=0; iandlt;512; i++){for (j=0; jandlt;512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is:a)0b)2048c)16384d)262144Correct answer is option 'C'. Can you explain this answer? - EduRev Computer Science Engineering (CSE) Question

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A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.
P1:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[i] [j];
}
}
P2:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[j] [i];
}
}
P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M₁ and that for P2 be M₂.
The value of M₁ is:

a)
0
b)
2048
c)
16384
d)
262144

Correct answer is option 'C'. Can you explain this answer?

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A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppos...

Code being C implies array layout is row-major.
When A[0][0] is fetched, 128 consecutive bytes are moved to cache. So, for the next 128/8 -1= 15 memory references
there won't be a cache miss. For the next iteration of i loop also the same thing happens as there is no temporal locality in the code. So, number of cache misses for P1
= (512/16) × 512
= 32 × 512
= 2¹⁴ = 16384

Hence, answer = option C

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A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio

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A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is:a)0b)2048c)16384d)262144Correct answer is option 'C'. Can you explain this answer?

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A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is:a)0b)2048c)16384d)262144Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is:a)0b)2048c)16384d)262144Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is:a)0b)2048c)16384d)262144Correct answer is option 'C'. Can you explain this answer?.

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