All Courses
Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity Get the App Login Join for Free
Sign in Open App
Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  In a virtual memory system, size of virtual a... Start Learning for Free
SaveJoin the Discussion on the App
In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?
  • a)
    2
  • b)
    10
  • c)
    12
  • d)
    14
Correct answer is option 'D'. Can you explain this answer?
FREE This question is part of
Download PDF Attempt Test
Download PDF Attempt this Test
Verified Answer
In a virtual memory system, size of virtual address is 32-bit, size of...
Virtual memory = 232 bytes Physical memory = 230 bytes 
Page size = Frame size = 4 * 103 bytes = 22 * 210 bytes = 212 bytes 
Number of frames = Physical memory / Frame size = 230/212 = 218 
Therefore, Numbers of bits for frame = 18 bits 
Page Table Entry Size = Number of bits for frame + Other information Other information = 32 - 18 = 14 bits 
 
Thus, option (D) is correct. 
 
Please comment below if you find anything wrong in the above post.
View all questions of this test
Most Upvoted Answer
In a virtual memory system, size of virtual address is 32-bit, size of...
Virtual Memory System with 32-bit Virtual Address and 30-bit Physical Address

Virtual address size = 32-bit
Physical address size = 30-bit
Page size = 4 Kbyte
Size of each page table entry = 32-bit

To determine the maximum number of bits that can be used for storing protection and other information in each page table entry, we need to calculate the number of bits required to represent the page offset and the page number.

Page Offset Calculation

Since the page size is 4 Kbyte, the page offset requires 12 bits (2^12 = 4 Kbyte). Therefore, the lower 12 bits of the virtual address are used to represent the page offset.

Page Number Calculation

To determine the number of bits required to represent the page number, we need to calculate the maximum number of pages in the virtual address space and physical address space.

Maximum number of pages in virtual address space = (2^32) / (2^12) = 2^20
Maximum number of pages in physical address space = (2^30) / (2^12) = 2^18

Since the virtual address space has a larger number of pages, we need 20 bits to represent the page number in the virtual address space. However, since the physical address space has a smaller number of pages, we only need 18 bits to represent the page number in the physical address space.

Therefore, the remaining 32 - 12 - 20 = 0 bits are available for storing protection and other information in each page table entry.

Answer: d) 14
< Previous Question Next Question >
Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 000400000, and a stack page starting at virtual address 0FFFFF000. The amount of memory required for storing the page tables of this process is

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

Top Courses for Computer Science Engineering (CSE)View all

Top Courses for Computer Science Engineering (CSE)

In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer?
Question Description
In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer?.
Solutions for In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer?, a detailed solution for In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? has been provided alongside types of In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?a)2b)10c)12d)14Correct answer is option 'D'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
Explore Courses for Computer Science Engineering (CSE) exam

Top Courses for Computer Science Engineering (CSE)

Explore Courses

Suggested Free Tests

Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
10M+ students study on EduRev
Get App
© EduRev
Education Revolution
Follow Us
Signup to see your scores go up within 7 days!
Access 1000+ FREE Docs, Videos and Tests
Takes less than 10 seconds to signup