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A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
- a)11 bits
- b)13 bits
- c)15 bits
- d)20 bits
Correct answer is option 'C'. Can you explain this answer?
Verified Answer
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The p...
Virtual Memory would not be very effective if every memory address had to be translated by looking up the associated physical page in memory. The solution is to cache the recent translations in a Translation Lookaside Buffer (TLB). A TLB has a fixed number of slots that contain page table entries, which map virtual addresses to physical addresses.
Solution Size of a page = 4KB = 2^12 means 12 offset bits CPU generates 32-bit virtual addresses Total number of bits needed to address a page frame = 32 - 12 = 20 If there are ‘n’ cache lines in a set, the cache placement is called n-way set associative. Since TLB is 4 way set associative and can hold total 128 (2^7) page table entries, number of sets in cache = 2^7/4 = 2^5. So 5 bits are needed to address a set, and 15 (20 - 5) bits are needed for tag. Option (C) is the correct answer.
Solution Size of a page = 4KB = 2^12 means 12 offset bits CPU generates 32-bit virtual addresses Total number of bits needed to address a page frame = 32 - 12 = 20 If there are ‘n’ cache lines in a set, the cache placement is called n-way set associative. Since TLB is 4 way set associative and can hold total 128 (2^7) page table entries, number of sets in cache = 2^7/4 = 2^5. So 5 bits are needed to address a set, and 15 (20 - 5) bits are needed for tag. Option (C) is the correct answer.
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A CPU generates 32-bit virtual addresses. The page size is 4 KB. The p...
TLB and Page Table
Translation look-aside buffer (TLB) is a hardware cache used by modern CPUs to reduce the time needed to access memory. It stores the most recently used page table entries (PTEs) in a cache to speed up the virtual-to-physical address translation process. The page table is a data structure used by the operating system to store information about the mapping between virtual and physical memory.
Given Parameters
- CPU generates 32-bit virtual addresses.
- Page size is 4 KB.
- TLB can hold a total of 128 page table entries.
- TLB is 4-way set associative.
Calculation
- Page offset: Since the page size is 4 KB (2^12), the last 12 bits of the virtual address will be the page offset.
- Page number: The remaining 20 bits will be used to represent the page number.
- TLB entries: The TLB can hold 128 PTEs, which means it can store 128 different page numbers.
- Set associativity: The TLB is 4-way set associative, which means each set can store up to 4 PTEs.
- Tag size: To determine the minimum size of the TLB tag, we need to calculate the number of bits required to represent the page number in the TLB.
- Total number of TLB entries = 128
- Number of sets = Total number of TLB entries / Associativity = 128 / 4 = 32
- Number of bits required to represent set index = log2(32) = 5
- Number of bits required to represent page offset = 12
- Number of bits required to represent page number = 32 - 5 - 12 = 15
Therefore, the minimum size of the TLB tag is 15 bits (option C).
Translation look-aside buffer (TLB) is a hardware cache used by modern CPUs to reduce the time needed to access memory. It stores the most recently used page table entries (PTEs) in a cache to speed up the virtual-to-physical address translation process. The page table is a data structure used by the operating system to store information about the mapping between virtual and physical memory.
Given Parameters
- CPU generates 32-bit virtual addresses.
- Page size is 4 KB.
- TLB can hold a total of 128 page table entries.
- TLB is 4-way set associative.
Calculation
- Page offset: Since the page size is 4 KB (2^12), the last 12 bits of the virtual address will be the page offset.
- Page number: The remaining 20 bits will be used to represent the page number.
- TLB entries: The TLB can hold 128 PTEs, which means it can store 128 different page numbers.
- Set associativity: The TLB is 4-way set associative, which means each set can store up to 4 PTEs.
- Tag size: To determine the minimum size of the TLB tag, we need to calculate the number of bits required to represent the page number in the TLB.
- Total number of TLB entries = 128
- Number of sets = Total number of TLB entries / Associativity = 128 / 4 = 32
- Number of bits required to represent set index = log2(32) = 5
- Number of bits required to represent page offset = 12
- Number of bits required to represent page number = 32 - 5 - 12 = 15
Therefore, the minimum size of the TLB tag is 15 bits (option C).
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A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer?
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A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2025 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2025 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer?.
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2025 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2025 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:a)11 bitsb)13 bitsc)15 bitsd)20 bitsCorrect answer is option 'C'. Can you explain this answer?.
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