All Courses
Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity Get the App Login Join for Free
Sign in Open App
Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  Consider a system using paging and segmentati... Start Learning for Free
Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.
How many bits in the virtual address specify the entire virtual address?
  • a)
    8 bits
  • b)
    16 bits
  • c)
    32 bits
  • d)
    64 bits
Correct answer is option 'C'. Can you explain this answer?
Clear all your Computer Science Engineering (CSE) doubts with EduRev
Verified Answer
Consider a system using paging and segmentation. The virtual address s...
View all questions of this test
Most Upvoted Answer
Consider a system using paging and segmentation. The virtual address s...
Explanation:

To determine the number of bits in the virtual address that specify the entire virtual address, we need to consider the size of the virtual address space and the page size.

Given:

- The virtual address space consists of up to 8 segments, each of length 229 bytes.
- The hardware pages each segment into 28 byte pages.

To calculate the size of the virtual address space, we can use the formula:

Virtual address space size = (number of segments) x (segment size)

= 8 x 229 bytes

= 1832 bytes

Since each segment is divided into 28 byte pages, the number of pages in each segment is:

Number of pages = (segment size) / (page size)

= 229 bytes / 28 bytes

= 8.18 pages

Since we cannot have a fractional number of pages, we round this up to 9 pages per segment.

Therefore, the total number of pages in the virtual address space is:

Total number of pages = (number of segments) x (number of pages per segment)

= 8 x 9

= 72 pages

Since each page is 28 bytes, the size of the page table is:

Page table size = (number of pages) x (page table entry size)

= 72 x 4 bytes

= 288 bytes

Now, we need to determine the number of bits required to address the entire virtual address space. We can do this by finding the smallest power of 2 that is greater than or equal to the virtual address space size:

2^11 = 2048

2^12 = 4096

Since the virtual address space size is between 2048 and 4096, we need at least 12 bits to address the entire virtual address space.

Therefore, the correct answer is option (c) 32 bits.
Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 000400000, and a stack page starting at virtual address 0FFFFF000. The amount of memory required for storing the page tables of this process is

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

Top Courses for Computer Science Engineering (CSE)View all

Top Courses for Computer Science Engineering (CSE)

Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer?
Question Description
Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2025 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2025 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer?.
Solutions for Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer?, a detailed solution for Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? has been provided alongside types of Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice Consider a system using paging and segmentation. The virtual address space consist of up to 8 segments and each segment is 229 bytes long. The hardware pages each segment into 28 byte pages.How many bits in the virtual address specify the entire virtual address?a)8 bitsb)16 bitsc)32 bitsd)64 bitsCorrect answer is option 'C'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
Explore Courses for Computer Science Engineering (CSE) exam

Top Courses for Computer Science Engineering (CSE)

Explore Courses
SaveJoin the Discussion on the App for FREE
Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
10M+ students study on EduRev
Get App
© EduRev
Education Revolution
Signup to see your scores go up within 7 days!
Access 1000+ FREE Docs, Videos and Tests
Takes less than 10 seconds to signup