Designing an Interface between 8086 CPU and Memory Chips

Introduction

In this task, we will design an interface between the 8086 CPU and four chips of 8K x 8 EPROM and two chips of 32 x 8 RAM. We will also select a suitable map for EPROM and ensure that the RAM address starts from 00000H to contain the Interrupt vector table.

EPROM Map Selection

For the four chips of 8K x 8 EPROM, we will select the following memory map:

- Starting address: 00000H
- Ending address: 1FFFFH
- Size of the memory space: 20000H

This map will allow us to address up to 32KB of memory space using four chips of 8K x 8 EPROM.

RAM Addressing

For the two chips of 32 x 8 RAM, we will ensure that the RAM address starts from 00000H so that it can contain the Interrupt vector table. The RAM will be mapped as follows:

- Starting address: 00000H
- Ending address: 03FFFH
- Size of the memory space: 04000H

This map will allow us to address up to 16KB of memory space using two chips of 32 x 8 RAM.

Chip Decoding Logic

To decode the chip select signals for the EPROM and RAM chips, we will use the following logic:

- A15-A13 will be used to select the EPROM chip.
- A15-A14 will be used to select the RAM chip.

The chip select signals for the EPROM and RAM chips will be generated as follows:

- EPROM chip select: CS = (A15-A13)’
- RAM chip select: CS = (A15-A14)’

Using this logic, we can ensure that the appropriate chip is selected when a memory access is requested by the CPU.

Conclusion

In this task, we have designed an interface between the 8086 CPU and memory chips. We have selected a suitable map for the EPROM and ensured that the RAM address starts from 00000H to contain the Interrupt vector table. We have also provided the chip decoding logic to ensure that the appropriate chip is selected when a memory access is requested by the CPU.

It is required to interface two chips of 32K*8 and four chips of 32K*8 RAM with 8086