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Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?
  • a)
    645 nanoseconds
  • b)
    1050 nanoseconds
  • c)
    1215 nanoseconds
  • d)
    1230 nanoseconds
Correct answer is option 'D'. Can you explain this answer?
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Consider a system with a two-level paging scheme in which a regular me...
Please note that page fault rate is given one page fault per 10,000 instructions. Since there are two memory accesses per instruction, so we need double address translation time for average instruction execution time. Also, there are 2 page table accessed if TLB miss occurred. TLB access assumed as 0. Therefore, Average Instruction execution time = Average CPU execution time + Average time for getting data(instruction operands from memory for each instruction) = Average CPU execution time + Average address translation time for each instruction + Average memory fetch time for each instruction + Average page fault time for each instruction = 100 + 2×(0.9×(0)+0.1×(2×150)) + 2×150 + 1 /10000 × 8 × 106 = 100 + 60 + 300 + 800 = 1260 ns So, none option is correct.
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Consider a system with a two-level paging scheme in which a regular me...
Understanding the Problem
To find the effective average instruction execution time, we need to consider the different scenarios that can occur during memory accesses, including TLB hits, TLB misses, and page faults.
Parameters Given
- Regular memory access time: 150 ns
- Page fault servicing time: 8 ms (or 8,000,000 ns)
- Average instruction time: 100 ns
- Memory accesses per instruction: 2
- TLB hit ratio: 90% (0.9)
- Page fault rate: 1 in 10,000 instructions (0.0001)
Calculating Effective Instruction Execution Time
1. TLB Hit Scenario:
- TLB hit time: 2 accesses x 150 ns = 300 ns
- Total time for TLB hit instruction: 100 ns (instruction) + 300 ns (memory) = 400 ns
2. TLB Miss Scenario:
- TLB miss time: 2 accesses x 150 ns + 150 ns (for page table access) = 450 ns
- Total time for TLB miss instruction: 100 ns + 450 ns = 550 ns
3. Page Fault Scenario:
- Page fault time: 8,000,000 ns
- Total time for page fault instruction: 100 ns + 8,000,000 ns = 8,000,100 ns
Calculating Average Execution Time
Using the probabilities:
- TLB hit: 0.9
- TLB miss: 0.1 (1 - TLB hit ratio)
- Page fault: 0.0001 (1 in 10,000)
Let’s calculate the effective average time:
- TLB hit contribution: 0.9 * 400 ns = 360 ns
- TLB miss contribution: 0.1 * 550 ns = 55 ns
- Page fault contribution: 0.0001 * 8,000,100 ns = 800 ns
Final Calculation
Effective average instruction execution time = 360 ns + 55 ns + 800 ns = 1215 ns.
Thus, the correct answer is option 'D' - 1230 nanoseconds.
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An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split theID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________. Correct answer is '1.54'. Can you explain this answer?

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Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?a)645 nanosecondsb)1050 nanosecondsc)1215 nanosecondsd)1230 nanosecondsCorrect answer is option 'D'. Can you explain this answer?
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