The typical quiescent power dissipation of low-power CMOS units is 2 nW.

Explanation:
CMOS (Complementary Metal-Oxide-Semiconductor) technology is widely used in low-power digital circuits due to its ability to minimize power consumption while providing high performance. The power dissipation of a CMOS unit refers to the amount of power it consumes when it is in a quiescent state, i.e., when there is no significant input activity or output load.

The quiescent power dissipation of a CMOS unit primarily depends on two factors: leakage currents and subthreshold leakage. Leakage currents occur due to the imperfect insulation between the different components of the CMOS device, causing a small amount of current to flow even when the device is not actively switching. Subthreshold leakage, on the other hand, refers to the small amount of current that flows through the channel of a transistor when it is in the off state.

Since low-power CMOS units are designed to minimize power consumption, they are optimized to reduce both leakage currents and subthreshold leakage. This optimization is achieved by using various techniques such as transistor sizing, threshold voltage scaling, and optimizing the device architecture.

The typical quiescent power dissipation of low-power CMOS units is 2 nW. This value is achieved by carefully balancing the trade-offs between power consumption and performance. By keeping the power dissipation at such a low level, low-power CMOS units are able to operate efficiently in battery-powered devices and other applications where power efficiency is crucial.

In summary, the typical quiescent power dissipation of low-power CMOS units is 2 nW. This low power consumption is achieved by minimizing leakage currents and subthreshold leakage through careful design and optimization techniques.