To eliminate the carry look ripple delay in an adder circuit, we can use a carry-look ahead adder (CLA). The carry look ripple delay occurs when the carry generated at each stage of the adder has to propagate through all the subsequent stages, resulting in a delay in the final sum and carry outputs.

A carry-look ahead adder is designed to reduce this delay by generating the carry signals for each stage in parallel, rather than sequentially. This allows the carry signals to be available at the same time as the input signals, reducing the overall delay.

Let's understand how a carry-look ahead adder works:

1. Full Adder:
A full adder is a combinational circuit that adds three inputs - two bits to be added (A and B) and a carry-in (Cin) from the previous stage. It produces a sum (S) and a carry-out (Cout) for the current stage.

2. Ripple Carry Adder:
A ripple carry adder is built by cascading multiple full adders, where the carry-out of each stage is connected to the carry-in of the next stage. The carry ripple delay occurs because the carry signals have to propagate through each stage sequentially.

3. Carry Look Ahead Adder:
In a carry-look ahead adder, the carry signals for each stage are generated independently of the input signals using a set of logic gates. This allows the carry signals to be computed in parallel, eliminating the ripple delay.

The carry-look ahead adder consists of two main parts:

a) Carry Generate (G) and Propagate (P) signals:
The carry generate (G) signal for each stage is computed as G = A AND B, i.e., the carry is generated if both input bits are 1. The carry propagate (P) signal for each stage is computed as P = A XOR B, i.e., the carry is propagated if either of the input bits is 1.

b) Carry Look Ahead Logic:
The carry look ahead logic combines the G and P signals to generate the final carry outputs for each stage. It uses the following equations:

C0 = Cin
Gi = Ai AND Bi
Pi = Ai XOR Bi
Ci+1 = Gi + (Pi AND Ci)

Here, Ci is the carry-in for stage i, and Ci+1 is the carry-out for stage i.

By computing the carry signals in parallel using the carry look ahead logic, the carry-look ahead adder eliminates the carry ripple delay.

Therefore, the correct answer is option D - Carry-look ahead adder.