Given information:
- 4-bit serial in parallel out shift register
- Initial state of register = 1111
- Input data = 1010
- 3 clock cycles passed

To find:
- Output of shift register after 3 clock cycles

Solution:
The given shift register is a serial in parallel out register, which means that data is entered into the register bit by bit serially, but the output is taken in parallel form.

The initial state of the register is 1111, which means that all the four bits are in the high state.

The input data is 1010, which means that the first bit is 1, second bit is 0, third bit is 1 and fourth bit is 0.

The data is entered into the shift register serially, starting from the leftmost bit. So, the first clock cycle will shift the initial state of the register to the left by one bit and the first bit of the input data will be entered into the rightmost bit of the register.

After the first clock cycle, the register will have the following state:
- 1111 (initial state) -> 1110 (after 1 clock cycle)

In the second clock cycle, the same process will be repeated and the second bit of the input data will be entered into the rightmost bit of the register.

After the second clock cycle, the register will have the following state:
- 1110 (state after 1 clock cycle) -> 1101 (after 2 clock cycles)

In the third clock cycle, the same process will be repeated and the third bit of the input data will be entered into the rightmost bit of the register.

After the third clock cycle, the register will have the following state:
- 1101 (state after 2 clock cycles) -> 1010 (after 3 clock cycles)

So, the output of the shift register after 3 clock cycles will be 1010, which is the same as the input data.

Therefore, the correct answer is option B (0101).