The given problem involves a 4-bit parallel out shift register that is initially clear. The bit sequence 1101 is serially entered into the shift register. We need to determine the output after two clock pulses.

To solve this problem, we can analyze the operation of the shift register step by step.

Initial State:
The shift register is initially clear, which means all its flip-flops are in the reset state. Therefore, the outputs of the shift register are all zeros.

First Clock Pulse:
During the first clock pulse, the serial input bit 1 is entered into the shift register. This causes the existing bits in the shift register to shift to the right. The new bit enters the leftmost flip-flop, and the previous bit in the leftmost flip-flop exits through the serial output.

After the first clock pulse, the shift register contains the following bits:
Q3 = 1 (serial input bit)
Q2 = 0 (shifted from Q3)
Q1 = 1 (shifted from Q2)
Q0 = 0 (shifted from Q1)

Second Clock Pulse:
During the second clock pulse, the serial input bit 0 is entered into the shift register. Again, the existing bits shift to the right, and the new bit enters the leftmost flip-flop. The previous bit in the leftmost flip-flop exits through the serial output.

After the second clock pulse, the shift register contains the following bits:
Q3 = 0 (serial input bit)
Q2 = 1 (shifted from Q3)
Q1 = 0 (shifted from Q2)
Q0 = 1 (shifted from Q1)

Output:
The output of the shift register after two clock pulses is 0100, which matches option D. This means that the serially entered bit sequence 1101 has been parallelly stored in the shift register.

Therefore, the correct answer is option D (0100).