Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > Which of the given below options is/are FALSE...
Start Learning for Free
Which of the given below options is/are FALSE?
- a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.
- b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
- c)During DMA, both the CPU and DMA controller can be bus masters at the same time.
- d)Daisy chaining is used to assign priorities in attending interrupts.
Correct answer is option 'B,C'. Can you explain this answer?
| FREE This question is part of | Download PDF Attempt this Test |
Most Upvoted Answer
Which of the given below options is/are FALSE?a)In polling, the CPU pe...
Option (A): TRUE
In the polling method, the CPU polls each device to check status bits to find out if the device has raised any interrupt. It is a software method.
Option (B): FALSE
In the vectored interrupt, a vector address is given to the CPU to identify the source of the interrupt. For example, in 8085μP, RST 4.5 is a vectored interrupt. Here, 4.5 is the interrupt vector which gives the vector address as 4.5 × 8 = (36)10 = (0024)16.
Option (C): FALSE
In DMA mode, either the CPU or the DMA controller would gain control of the system bus time, but not both. Accordingly, the CPU would be either in a busy state or a Hold state. It would be in a busy state until the I/O device prepares the data and would go to Hold state when the I/O device starts transferring data to the main memory via the DMA controller.
Option (D): TRUE
In the daisy-chaining method of interrupt handling, the devices are connected serially in such a manner that the nearest device to the CPU has the highest priority, followed by the next device and so on.
Hence, the correct options are (B) and (C).
Attention Computer Science Engineering (CSE) Students!
To make sure you are not studying endlessly, EduRev has designed Computer Science Engineering (CSE) study material, with Structured Courses, Videos, & Test Series. Plus get personalized analysis, doubt solving and improvement plans to achieve a great score in Computer Science Engineering (CSE).
|
Explore Courses for Computer Science Engineering (CSE) exam
|
|
Similar Computer Science Engineering (CSE) Doubts
Top Courses for Computer Science Engineering (CSE)View all
Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer?
Question Description
Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer?.
Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer?.
Solutions for Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE).
Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of
Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer?, a detailed solution for Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? has been provided alongside types of Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? theory, EduRev gives you an
ample number of questions to practice Which of the given below options is/are FALSE?a)In polling, the CPU periodically checks the status bits to know if any device needs its attention.b)When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.c)During DMA, both the CPU and DMA controller can be bus masters at the same time.d)Daisy chaining is used to assign priorities in attending interrupts.Correct answer is option 'B,C'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
|
|
Explore Courses for Computer Science Engineering (CSE) exam
|
|
Suggested Free Tests
Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
|
© EduRev
|
Education Revolution
|
Follow Us
|
Signup to see your scores
go up within 7 days!
Access 1000+ FREE Docs, Videos and Tests
Takes less than 10 seconds to signup