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Addressing of a 32 K × 16 memory is realized using a single decoder. The minimum number of AND gate required for the decoder is
- a)28
- b)232
- c)215
- d)219
Correct answer is option 'C'. Can you explain this answer?
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Most Upvoted Answer
Addressing of a 32 K × 16 memory is realized using a single decoder. ...
Explanation:
Addressing of a 32 K × 16 memory is realized using a single decoder. The given memory consists of 32K words, where each word is of 16 bits.
The number of address lines required to address 32K words = log2(32K) = 15
Hence, there are 15 address lines required to address the memory.
A single decoder with n input lines can decode 2^n output lines.
In this case, we need to decode 2^15 output lines using a single decoder.
Therefore, the minimum number of AND gates required for the decoder can be calculated as follows:
Number of AND gates = (Number of output lines) x (Number of input lines)
Number of input lines = 15 (as we have 15 address lines in this case)
Number of output lines = 2^15 = 32,768
Therefore, the minimum number of AND gates required for the decoder = 15 x 2^15 = 215
Hence, option C is the correct answer.
Addressing of a 32 K × 16 memory is realized using a single decoder. The given memory consists of 32K words, where each word is of 16 bits.
The number of address lines required to address 32K words = log2(32K) = 15
Hence, there are 15 address lines required to address the memory.
A single decoder with n input lines can decode 2^n output lines.
In this case, we need to decode 2^15 output lines using a single decoder.
Therefore, the minimum number of AND gates required for the decoder can be calculated as follows:
Number of AND gates = (Number of output lines) x (Number of input lines)
Number of input lines = 15 (as we have 15 address lines in this case)
Number of output lines = 2^15 = 32,768
Therefore, the minimum number of AND gates required for the decoder = 15 x 2^15 = 215
Hence, option C is the correct answer.
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Community Answer
Addressing of a 32 K × 16 memory is realized using a single decoder. ...
Given
Addressing of memory = 32 K × 16
Addressing of memory = 25 ×210×16 (Q K =210 )
Addressing of memory = 215 ×16
So 32 K × 16 memory needs 15 address lines
So it will need decoder of size 15 × 215 , which will need 215 AND gates.
Hence, the correct option is (C).
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