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Consider a system with byte-addressable memory, 31 bit logical addresses, 4 kilobyte page size and page table entries of 4 bytes each. The size of the page table in the system in megabytes is _____?
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Consider a system with byte-addressable memory, 31 bit logical address...
Calculating the Size of the Page Table


To calculate the size of the page table, we need to consider the number of pages and the size of each page table entry.

Calculating the Number of Pages


The logical address space is given as 31 bits, which means we have a total of 2^31 possible logical addresses.

Since the page size is 4 kilobytes, we can calculate the number of pages as follows:
Number of pages = (Total logical address space) / (Page size)
= (2^31) / (4 * 1024)
= (2^31) / (2^12)
= 2^31-12
= 2^19

Therefore, we have a total of 2^19 pages in the system.

Calculating the Size of Each Page Table Entry


The size of each page table entry is given as 4 bytes.

Calculating the Size of the Page Table


To calculate the size of the page table, we multiply the number of pages by the size of each page table entry:
Size of page table = (Number of pages) * (Size of each page table entry)
= (2^19) * (4 bytes)
= (2^19) * (4 * 8 bits)
= (2^19) * (32 bits)
= (2^19) * (2^5)
= 2^24 bytes

Since we are asked to express the size of the page table in megabytes, we can convert the size to megabytes as follows:
Size of page table in megabytes = (Size of page table) / (2^20)
= (2^24 bytes) / (2^20 bytes)
= 2^4
= 16 megabytes

Therefore, the size of the page table in the system is 16 megabytes.
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A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

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Consider a system with byte-addressable memory, 31 bit logical addresses, 4 kilobyte page size and page table entries of 4 bytes each. The size of the page table in the system in megabytes is _____?
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