The maximum gate delay for any output to appear in an array multiplier for multiplying two bit numbers isa)b)c)d)Correct answer is option 'B'. Can you explain this answer? - EduRev Computer Science Engineering (CSE) Question

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The maximum gate delay for any output to appear in an array multiplier for multiplying two bit numbers is

Correct answer is option 'B'. Can you explain this answer?

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The maximum gate delay for any output to appear in an array multiplier...

In a N X M array multiplier we have N * M AND gates and (M-1) N bit adders used.
Total delay in N X M (N>=M) array multiplier due to AND gate in partial products at all level is just 1 unit AND gate delay as the operation is done parallel wise at each step. Now delays at level 1 to (M-1) is = (M-1)*delay due to 1 unit of N bit adder. Therefore the maximum gate delay is O(M) but here M=N therefore O(N).

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