RISC (Reduced Instruction Set Computing) architecture is power efficient.

Explanation:

RISC and CISC (Complex Instruction Set Computing) are two different types of computer architectures. The main difference between them is the number of instructions that they use to perform a task. While CISC uses a large number of complex instructions, RISC uses a smaller number of simple instructions.

The power efficiency of a processor is determined by its ability to perform tasks while consuming less power. RISC architecture is power efficient because of the following reasons:

1. Smaller Instruction Set: RISC architecture uses a smaller instruction set, which means that the processor can execute instructions faster and with less power.

2. Pipelining: RISC architecture uses pipelining, which allows the processor to execute multiple instructions simultaneously. This reduces the amount of time it takes to execute a program and reduces power consumption.

3. Reduced Memory Access: RISC architecture reduces memory access, which reduces power consumption. The instructions are designed to work with registers, which are located on the processor. This reduces the need to access memory, which consumes more power.

4. Lower Complexity: RISC architecture is less complex than CISC architecture, which means that it requires less power to operate. The simpler design of RISC architecture allows for faster execution of instructions, which reduces power consumption.

In conclusion, RISC architecture is power efficient due to its smaller instruction set, pipelining, reduced memory access, and lower complexity.