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In a system with 32 bit virtual addresses and 1 KB page size, use of one-level page tables for virtual to physical address translation is not practical because of
  • a)
    the large amount of internal fragmentation
  • b)
    the large amount of external fragmentation
  • c)
    the large memory overhead in maintaining page tables
  • d)
    the large computation overhead in the translation process
Correct answer is option 'C'. Can you explain this answer?
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Verified Answer
In a system with 32 bit virtual addresses and 1 KB page size, use of o...
Correct option C
Number of entries in page table =
                    (virtual address space size)/(page size)
                    = (2^32)/(2^10) 
                    = 2^22
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Most Upvoted Answer
In a system with 32 bit virtual addresses and 1 KB page size, use of o...
Explanation:

Virtual to physical address translation is an important aspect of memory management in computer systems. One way to perform this translation is by using page tables, which map virtual pages to physical pages. In a system with 32 bit virtual addresses and 1 KB page size, one-level page tables are not practical for virtual to physical address translation for the following reasons:

Large memory overhead in maintaining page tables:
- One-level page tables require a single table that contains all the entries for the entire virtual address space.
- In a system with 32 bit virtual addresses and 1 KB page size, the virtual address space is 2^32 bytes, which requires 2^20 entries in the page table.
- Each entry in the page table requires at least 4 bytes (to store the physical page number), so the total size of the page table is at least 4 MB.
- This is a large memory overhead, especially considering that not all entries in the page table will be used.

Fragmentation:
- One-level page tables can suffer from external fragmentation, where there are free physical pages but they are not contiguous.
- This can result in wasted memory, as a virtual page may not be able to be mapped to a contiguous set of physical pages.
- However, this is not the main reason that one-level page tables are not practical in this case.

Computation overhead:
- One-level page tables require a linear search through the page table to find the entry corresponding to a given virtual address.
- In a system with 2^32 byte virtual address space and 1 KB page size, this requires at least 2^20 memory accesses to find the corresponding physical page.
- This is a large computation overhead, especially considering that this operation will be performed frequently.

Therefore, the main reason that one-level page tables are not practical in this case is the large memory overhead in maintaining page tables.
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A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 000400000, and a stack page starting at virtual address 0FFFFF000. The amount of memory required for storing the page tables of this process is

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

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In a system with 32 bit virtual addresses and 1 KB page size, use of one-level page tables for virtual to physical address translation is not practical because ofa)the large amount of internal fragmentationb)the large amount of external fragmentationc)the large memory overhead in maintaining page tablesd)the large computation overhead in the translation processCorrect answer is option 'C'. Can you explain this answer?
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