Biasing FET | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

BIASING FET:-

   For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stable in the central portion of the pinch off region. The Q point should be independent of device parameter variations and ambient temperature variations.

This can be achieved by suitably selecting the gate to source voltage V_GS and drain current I_D which is referred to as biasing

   JFET biasing circuits are very similar to BJT biasing circuits. The main difference between JFET circuits and BJT circuits is the operation of the active components themselves.

        There are mainly two types of Biasing circuits

1. Self bias
2. Voltage divider bias.

7.3.1. SELF BIAS:-

Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate.

                        A  self bias circuit is shown in the fig 7.3

Self bias is the most common type of JFET bias. This JFET must be operated such that gate source junction is always reverse biased. This condition requires a negative V_GS for an N-channel JFET and a positive V_GS for P-channel JFET. This can be achieved using the self bias arrangement as shown in Fig 7.3. The gate resistor R_G doesn’t affect the bias because it has essentially no voltage drop across it, and the gate remains at 0V. R_G is necessary only to isolate an ac signal from ground in amplifier applications. The voltage drop across resistor R_S makes gate source junction reverse biased.

DC analysis of self Bias:-

In the following DC analysis , the N-channel JFET shown in the fig7.4. is used for illustration.

For DC analysis, we can replace coupling capacitors by open circuits and we can also replace the resistor R_G by a short circuit equivalent.

:. I_G = 0

The relation between I_D and V_GS is given by-

             I_D=I_dss 

VGS for N channel JFET is =-I_D R_S

Substuting  this value in the above equation

For the N-chanel FET in the above figure

Is produces a voltage drop across Rs and makes the source positive w.r.t ground

in any JFET circuit all the source current passes through the device to drain circuit this is due to the fact that there is no significant gate current

therefore we can define source current as Is=Id and Vg=0 then

Vs= Is Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawing the self bias line:-

Typical transfer characteristics for a self biased JFET are shown in the fig7.5.

The maximum drain current is 6mA and the gate source cut off voltage is -3V. This means the gate voltage has to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self bias line.

Let us assume RS = 500Ω

 With this Rs , we can plot two points corresponding to I_D = 0 and Id = I_DSS

      for I_D = 0

V_GS = -I_D RS

V_GS = 0 X (500.Ω) = 0V

So the first point is (0 ,0)

                                      ( I_d, V_GS)

For I_D= I_DSS=6mA

V_GS = (-6mA) (500 Ω) = -3V

So the 2^nd  Point will be (6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will intersect the transconductance curve and it is known as self bias line. The intersection point gives the operating point of the self bias JFET for the circuit.

At Q point , the ID is slightly  > than 2mA and VGS is slightly > -1V. The Q point for the self bias JFET depends on the value of Rs.If Rs is large, Q point far down on the transconductance curve ,ID is small, when Rs is small Q point is far up on the curve , ID is large.

VOLTAGE DIVIDER BIAS:-

The fig7.6 shows N channel JFET with voltage divider bias. The voltage at the source of JFET must be more positive than the voltage at the gate in order to keep the gate to source junction reverse biased. The source voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the voltage divider formula.

For dc analysis fig 7.7                        

Applying KVL to the input circuit

V_G-V_GS-V_S =0

:: V_GS = V_G-V_s=V_G-I_SR_S

V_GS = V_G-I_DR_S       :: I_S = I_D

Applying KVL to the input circuit we get

V_DS+I_DR_D+V_S-V_DD =0

::V_DS = V,-I_DR_D-I_DR,

V_DS = V_DD-I_D ( R_D +R_S )

The Q point of a JFET amplifier , using the voltage divider bias is 

I_DQ  = I_DSS [1-V_GS/V_P]2

V_DSQ = V_DD-ID ( R_D+R_S )

JFET AS A VVR OR VDR:-

Let us consider the drain characteristics of FET as shown in the fig.

In this characteristics we can see that in the region before pinch off voltage, drain characteristics are linear, i.e. FET operation is linear. In this region the FET is useful as a voltage controlled resistor, i.e. the drain to source resistance is controlled by the bias voltage V_GS.( In this region only FET behaves like an ordinary resistor. This resistances can be varied by V_GS). The operation of FET in the region is useful in most linear applications of FET. In such an application, the FET is also referred to as a voltage variable resistor (VVR) or voltage dependent resistor (VDR).

The drain to source conductance ( r_d )

                           g_d=     for small values of V_ds which may also be expressed as

                   g_d=g_d0

where g_d0 is the value of drain conductance.

When  the variation of the r_d with V_GS can be closely approximated by the expression

r_d=  Where r_o = drain resistance at zero gate bias. K = a constant, dependent upon FET type.

APPLICATION OF VVR:

The VVR property of FET can be used to vary the voltage gain of a multistage amplifier A, as the signal level is increased. This action is called AGC automatic gain control. A typical arrangement is shown in the fig.

Here maximum value of signal is taken rectified; filter to produce a DC voltage proportional to the output signal level. This voltage is applied to the gate of JFET, thus causing the resistance between drain and source to change. As this resistance is connected across R_E, so effective R_E also changes according to change in the drain to source resistance. When output signal level increases, the drain to source resistance r_d increases, increasing effective R_E. Increase in R_E causes the gain of transistor Q1 to decrease, reducing the output signal. Exactly reverse process takes place when output signal level is decreased.

:: The output signal level is maintained constant. It is to be noted that the DC bias conditions of Q1 are not affected by JFET since FET is isolated from Q1 by capacitor C2.