CMOS Flip Flop Video Lecture | Digital Electronics - Electrical Engineering (EE)

welcome to you know how in this video we
will look at how a flip-flop is
constructed before going into the
details about how it is constructed
using gates I would like to first draw
the symbol view for the flip-flop so a
flip-flop will have a D input and then
there is a Q out a Q output a D input
and now instead of enable which was
there for the latch it has a clock input
clock input so the way this is supposed
to function is so you have a clock
running and what the flip-flop does is
say you have data going this way
say this is an example for a data now if
you look at the rising edges of all the
clock here so this is clock and this is
D in and the output will look like this
so what it does is at every falling edge
it looks at what is the state of D in
and then puts that on the output so
assume that D ends was high the Q out
was high initially and so at the at this
rising edge the first rising edge of the
clock it sees that DN is low so it goes
low and then at the second rising edge
of the clock it doesn't care about what
DN is again till the next rising edge of
the clock and at the second rising edge
of the clock it sees that DN is still
low so it remains low and at the third
rising edge of the clock it sees that DN
is high now so it goes high so this is Q
out so a flip-flop is supposed to be
looking at only the rising edges of
clock it's not like a latch where it is
on an edge when the enable is high it
passes D into the output and when enable
is low it latches the data here it is
not like that it looks at it's only at
the rising edges of the clock it looks
at the data and puts it on the output or
it could be the other way too
so there could be another flip-flop
which has a clock bar as input so it
could be you can have a bubble here so
you can still say clock but now it looks
at the falling edges of the clock so you
have D in and then you have the Q output
so now it could be looking at the
falling edges of the clock so what what
I meant by that is now if you say your
clock is this way and I'm
King the falling edges and let's assume
that DN is something like this this is
Dean and this is Clark and then I will
sketch the Q out now so assume cured has
started at high initially at the falling
edge of the clock
the first falling edge of the clock beam
is low so it goes low
the second falling edge of the clock DN
is high so it goes high the output and
at the third falling edge of the clock
the output goes low again so this is Q R
so this is for this is for this case and
then this the bottom one is for this
case so you have the two flip flops one
is a rising edge triggered flip-flop
the first one is rising edge triggered
flip-flop rising edge triggered and the
second one is falling edge triggered so
these are all edge triggered so now
let's look at how the flip-flop can be
constructed okay so let's look at that
one here let me go here they got more
place to work with so flip flop is you
will be amazed to see that it can be
constructed using two latches so let's
draw the latch we looked at how a latch
is constructed so
these are the inverters of the latch the
two switches so this is the latch so you
have the D in here and the switch s1
switch s two inverters a and B and this
is the inverter one that brings in that
brings in your input so this is a latch
now what I do is and usually latches the
switches s1 was controlled by enable or
basically when enable is high s1 was
closed and s2 was closed when enable is
low so you can say enable bar so that is
what it was now let's see later first
now what I will do is to complete the
flip-flop I will add another latch in
series to this so the output of the
first latch is connected to say a second
latch here
so I forgot to put a switch in between
these two so that switch needs to be
there so there is a switch
this is s1 Prime and then s2 prime then
this connects goes and connects back
here so you got to you got to the
latches connected in series now the way
we use we control the switches is
let's do s1 is closed when clock is low
or clogged bar or clogged B and then s2
is closed when clock is high so s1 is
closed s1 is closed when clock is lower
to our bar is high and s2 is closed when
clock is high now this one here s1 prime
is clock will be closed when clock is
high it is similar to s2 and s2 prime
will be closed when clock is low or
clock bar is high
so now let's see how this works so now
what happens is so now let me write this
here so s1 and s2 prime or closed when
clock is low and s2 and s1 prime or
closed when clock is high so now looks
like we need to actually draw these -
you know cases and so see how how this
works
so let's redraw these cases with the
switches in the two different conditions
so the first condition when we will save
and close
work is high when clock is high so if
you go back and look at it we said when
clock is high this switch is closed and
this switch is closed so TN and then you
have the inverter the switch is open and
now the feedback in the first latch is
closed then you got now let me use a
different color here for this one so now
you have this now in this case now this
switch is closed and the feedback is
open here so this is open so now what's
happening here is now in this case so D
in so DN would have come in and it is
latched in the first latch initially so
this latch it's latched in this and then
whatever is latched is going to the
output Q out now so in this case the Q
out has the value that was already
latched in the latch number one so
that's what is there when the clock is
high and now let me draw the case when
the clock is low when the clock is low
so now you have this closed and the
feedback in the first latch is open and
this one
you have this open here and the feedback
in the second one is closed so this is
closed so this is when clock is low when
clock is low so now what word it means
is let me put a green circle around the
latch that is closed so this is Q art
again so what what it is saying is when
clock is low you are bringing the D in
till this point here you're bringing the
D into the input of the second latch and
then when clock goes high you close you
close the second latch you store the D
in when the clock was low so the D in
here in this latch and then pass that on
to the output when the clock is high so
irrespective so even irrespective when
the clock is low or high even if Dean is
changing it is the Q out is only getting
the value at the rising edge of clock
why the rising edge of clock because if
you see at the rising edge of clock now
this is the clock and so let me try
falling into rising edge so in the when
the clock was low when the clock is low
this is the condition to and clock is
high at the condition 1 so this is
condition 2 and condition 1 so when the
clock is low DN came up to this point
here but it doesn't go all the way to Q
out it's waiting for the clock to go
high and then once the clock goes high
it goes into condition 1 and puts that
out at this rising edge you see a change
in Q R
but at the rising edge what also happens
is the first latch the in the condition
one if you see the green circle here it
is this the first latch latches the data
so it doesn't change anymore so it
always waits for the rising edge of the
clock and then that's when the cue out
changes so this is how a latch is
constructed using CMOS a CMOS devices so
it is constructed using two two latches
and then I had to say again that all
these pass gates all their switches are
really CMOS transmission gates all these
switches are CMOS transmission gates and
then there is a video that explains how
the CMOS transmission gate works so this
is how a flip-flop works