Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

Computer Architecture & Organisation (CAO)

Computer Science Engineering (CSE) : Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

The document Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev is a part of the Computer Science Engineering (CSE) Course Computer Architecture & Organisation (CAO).
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Design of Control Unit

  • The bits of the microinstruction are usually divided into fields, with each field defining a distinct, separate function.
  • The various fields encountered in instruction formats provide:
    • Control bits to initiate microoperations in the system
    • Special bits to specify the way that the next address is to be evaluated
    • An address field for branching
  • The number of control bits that initiate microoperations can be reduced by grouping mutually exclusive variables into fields by encoding the k bits in each field to provide 2microoperations.
  • Each field requires a decoder to produce the corresponding control signals.
    • Reduces the size of the microinstruction bits
    • Requires additional hardware external to the control memory
    • Increases the delay time of the control signals
  • Fig. 3-11 shows the three decoders and some of the connections that must be made from their outputs.
  • Outputs 5 or 6 of decoder F1 are connected to the load input of AR so that when either one of these outputs is active; information from the multiplexers is transferred to AR.
  • The transfer into AR occurs with a clock pulse transition only when output 5 (from DR (0-10) to AR i.e. DRTAR) or output 6 (from PC to AR i.e. PCTAR) of the decoder are active.  
  • The arithmetic logic shift unit can be designed instead of using gates to generate the control signals; it comes from the outputs of the decoders. 

Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

Microprogram Sequencer 

  • The basic components of a microprogrammed control unit are the control memory and the circuits that select the next address.
  • The address selection part is called a microprogram sequencer.
  • A microprogram sequencer can be constructed with digital functions to suit a particular application.
  • To guarantee a wide range of acceptability, an integrated circuit sequencer must provide an internal organization that can be adapted to a wide range of application.
  • The purpose of a microprogram sequencer is to present an address to the control memory so that a microinstruction may be read and executed.
  • The block diagram of the microprogram sequencer is shown in Fig. 3-12.
    • The control memory is included to show the interaction between the sequencer and the attached to it.
    • There are two multiplexers in the circuit; first multiplexer selects an address from one of the four sources and routes to CAR, second multiplexer tests the value of the selected status bit and result is applied to an input logic circuit.
    • The output from CAR provides the address for control memory, contents of CAR incremented and applied to one of the multiplexers input and to the SBR.
    • Although the diagram shows a single subroutine register, a typical sequencer will have a register stack about four to eight levels deep. In this way, a push, pop operation and stack pointer operates for subroutine call and return instructions.
    • The CD (Condition) field of the microinstruction selects one of the status bits in the second multiplexer.
    • The Test variable (either 1 or 0) i.e. T value together with the two bits from the BR (Branch) field go to an input logic circuit.
    • The input logic circuit determines the type of the operation.

Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

Design of Input Logic

  • The input logic in a particular sequencer will determine the type of operations that are available in the unit.
  • Typical sequencer operations are: increment, branch or jump, call and return from subroutine, load an external address, push or pop the stack, and other address sequencing operations
  • Based on the function listed in each entry was defined in Table 3-1, the truth table for the input logic circuit is shown in Table 3-4.
  • Therefore, the simplified Boolean functions for the input logic circuit can be given as:
    Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

Design of Control Unit Computer Science Engineering (CSE) Notes | EduRev

  • The bit values for S1 and S0 are determined from the stated function and the path in the multiplexer that establishes the required transfer.
  • Note that the incrementer circuit in the sequencer of Fig. 7-12 is not a counter constructed with flip-flops but rather a combinational circuit constructed with gates.
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