Loading Parallel Data Electrical Engineering (EE) Notes | EduRev

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Electrical Engineering (EE) : Loading Parallel Data Electrical Engineering (EE) Notes | EduRev

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If the Loading Parallel Data Electrical Engineering (EE) Notes | EduRev input is taken to logic 0, the LOAD control line connected to the four pairs of NAND gates associated with the four flip-flops will be at logic 1, and all four pairs of NAND gates will be enabled. Therefore a logic 1 appearing on any of the D inputs will be inverted by the NOT gate connected to the D input, making the inputs to the left hand NAND gate of the relevant pair of gates, logic 1 and logic 0. This will cause logic 1 to be applied to the Loading Parallel Data Electrical Engineering (EE) Notes | EduRev input of the flip-flop.

The right hand NAND gate of the pair will have both inputs at logic 1, due to the logic 1 on LOAD line and logic 1 on the D input, and so will output logic 0 (NAND qate rules) to the Loading Parallel Data Electrical Engineering (EE) Notes | EduRev input of the flip-flop, setting the Q output to logic 1.

If the D input is at logic 0, the left hand gate of the NAND gate pair will output logic 0 and the right hand NAND gate will output logic 1, causing the Loading Parallel Data Electrical Engineering (EE) Notes | EduRev input to clear the Q output of the relevant flip-flop to logic 0.

Notice that as JK flip-flops are being used in this design, a NOT qate is connected between J and K of the first flip-flop of the chain to make the JK flip-flop mimic a D Type. The remaining flip-flops of the shift register have J and K connected to the previous Q and Q outputs, so will also be at opposite logic states. 

 

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