MOSFET Biasing | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

 Page 1


 
 
 
 
 
Biasing of MOSFET 
  
N-channel enhancement mode MOSFET circuit shows the source terminal at 
ground potential and is common to both the input and output sides of the circuit. The 
coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to 
be coupled to the gate of the MOSFET 
  
 
Figure 1.8.1 N MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
  
As I
g
 = 0 in V
G
 is given as, 
 
 
  
Page 2


 
 
 
 
 
Biasing of MOSFET 
  
N-channel enhancement mode MOSFET circuit shows the source terminal at 
ground potential and is common to both the input and output sides of the circuit. The 
coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to 
be coupled to the gate of the MOSFET 
  
 
Figure 1.8.1 N MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
  
As I
g
 = 0 in V
G
 is given as, 
 
 
  
 
 
 
 
Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,  
 
 
PMOS Common Source Circuit 
 
 
 
Figure 1.8.2 P MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
 
Here, the source is tied to +VDD, Which become signal ground in the a.c. 
equivalent circuit. Thus it is also a common-source circuit. 
Page 3


 
 
 
 
 
Biasing of MOSFET 
  
N-channel enhancement mode MOSFET circuit shows the source terminal at 
ground potential and is common to both the input and output sides of the circuit. The 
coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to 
be coupled to the gate of the MOSFET 
  
 
Figure 1.8.1 N MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
  
As I
g
 = 0 in V
G
 is given as, 
 
 
  
 
 
 
 
Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,  
 
 
PMOS Common Source Circuit 
 
 
 
Figure 1.8.2 P MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
 
Here, the source is tied to +VDD, Which become signal ground in the a.c. 
equivalent circuit. Thus it is also a common-source circuit. 
 
 
 
 
The d.c. analysis for this circuit is essentially the same as for the n-channel MOSFET 
circuit. The gate voltage is given by, 
 
 
Load Line and Modes of Operation 
  
The load line gives a graphical picture showing the region in whichthe 
MOSFET is biased. Consider the common-source circuit shown in Figure 1.8.2 
Writing Kirchhoff's voltage law around the drain-source loop results V
Ds
 = V
DD
 -
I
DRD
, which is the load line equation. It shows a linear relationship between the drain 
current and drain-to-source voltage. Figure 1.8.3 shows the V
DS(sat)
 characteristic for 
the MOSFET 
Page 4


 
 
 
 
 
Biasing of MOSFET 
  
N-channel enhancement mode MOSFET circuit shows the source terminal at 
ground potential and is common to both the input and output sides of the circuit. The 
coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to 
be coupled to the gate of the MOSFET 
  
 
Figure 1.8.1 N MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
  
As I
g
 = 0 in V
G
 is given as, 
 
 
  
 
 
 
 
Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,  
 
 
PMOS Common Source Circuit 
 
 
 
Figure 1.8.2 P MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
 
Here, the source is tied to +VDD, Which become signal ground in the a.c. 
equivalent circuit. Thus it is also a common-source circuit. 
 
 
 
 
The d.c. analysis for this circuit is essentially the same as for the n-channel MOSFET 
circuit. The gate voltage is given by, 
 
 
Load Line and Modes of Operation 
  
The load line gives a graphical picture showing the region in whichthe 
MOSFET is biased. Consider the common-source circuit shown in Figure 1.8.2 
Writing Kirchhoff's voltage law around the drain-source loop results V
Ds
 = V
DD
 -
I
DRD
, which is the load line equation. It shows a linear relationship between the drain 
current and drain-to-source voltage. Figure 1.8.3 shows the V
DS(sat)
 characteristic for 
the MOSFET 
 
 
 
 
 
 
Figure 1.8.3 Common Source Circuit and its Transfer Characterictics 
Diagram Source Brain Kart 
 
 
  
The two end points of the load line are determine in the usual manner. If the 
drain current = 0, then V
DS
= 10 v; if V
DS
 = 0, then drain current = 10/40 = 0.25 mA. 
The Q-point of the MOSFET is given by the d.c. drain current (I
D
) and drain-to-
source voltage (V
DS
) and it is always on the load line, as shown in the Figure 1.8.3and 
1.8.4. 
  If the gate-to-source voltage is less than V1, the drain current is zero and the 
MOSFET is in cut-off. As the gate-to- source voltage becomes just greater than the 
Page 5


 
 
 
 
 
Biasing of MOSFET 
  
N-channel enhancement mode MOSFET circuit shows the source terminal at 
ground potential and is common to both the input and output sides of the circuit. The 
coupling capacitor acts as an open circuit to d.c. but it allows the signal voltage to 
be coupled to the gate of the MOSFET 
  
 
Figure 1.8.1 N MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
  
As I
g
 = 0 in V
G
 is given as, 
 
 
  
 
 
 
 
Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,  
 
 
PMOS Common Source Circuit 
 
 
 
Figure 1.8.2 P MOS Common Source Circuit and its DC equivalent 
Diagram Source Brain Kart 
 
 
Here, the source is tied to +VDD, Which become signal ground in the a.c. 
equivalent circuit. Thus it is also a common-source circuit. 
 
 
 
 
The d.c. analysis for this circuit is essentially the same as for the n-channel MOSFET 
circuit. The gate voltage is given by, 
 
 
Load Line and Modes of Operation 
  
The load line gives a graphical picture showing the region in whichthe 
MOSFET is biased. Consider the common-source circuit shown in Figure 1.8.2 
Writing Kirchhoff's voltage law around the drain-source loop results V
Ds
 = V
DD
 -
I
DRD
, which is the load line equation. It shows a linear relationship between the drain 
current and drain-to-source voltage. Figure 1.8.3 shows the V
DS(sat)
 characteristic for 
the MOSFET 
 
 
 
 
 
 
Figure 1.8.3 Common Source Circuit and its Transfer Characterictics 
Diagram Source Brain Kart 
 
 
  
The two end points of the load line are determine in the usual manner. If the 
drain current = 0, then V
DS
= 10 v; if V
DS
 = 0, then drain current = 10/40 = 0.25 mA. 
The Q-point of the MOSFET is given by the d.c. drain current (I
D
) and drain-to-
source voltage (V
DS
) and it is always on the load line, as shown in the Figure 1.8.3and 
1.8.4. 
  If the gate-to-source voltage is less than V1, the drain current is zero and the 
MOSFET is in cut-off. As the gate-to- source voltage becomes just greater than the 
 
 
 
 
threshold voltage, the MOSFET turns ON and is biased in the saturation region. As 
V 
GS
 increases, the Q-point moves up the load line. The transition point is the 
boundary between the saturation and non-saturation regions. It is the point where, 
 
 Common Source circuit for EMOSFET with source resistor 
 
Figure 1.8.4 N MOS Common Source Circuit with Source Resistor 
Diagram Source Brain Kart 
Voltage Divider Bias