Master Slave JK Flip Flop Video Lecture | Analog and Digital Electronics - Electrical Engineering (EE)

hey what's going on guys standby offer
simple snippets and welcome back to a
new video tutorial under digital
electronics and today's topic is going
to be master slave flip-flop in digital
electronics so this is sort of like the
most important flip-flop under the all
types of flip-flops that we've been
covering in this entire playlist and it
is really important that you understand
the race condition properly so in the
previous video of this playlist we
discussed in detail how the Rhys
condition happens the difference between
arrays and toggling and what exactly
happens behind the scenes when racing is
happening and then we also discussed
that there are three different ways in
which we can avoid the racing condition
and out of that one was to use master
slave flip-flop or master slave setup
and this video is all going to be about
master slave flip-flop and it's going to
be a little lengthy video because this
is a big concept and we will be covering
everything starting from the circuit
diagram to the truth table and then also
see how the toggling happens with the
use of graph and lose signal diagrams
okay so with that being said let's start
off with today's topic and I hope you
already have a good idea about JK
flip-flop and racing condition if not
you can check out the videos in this
playlist ok so as you can see on the
screen we have one JK flip-flop over
here right so this is that circuit now
how do we make a master slave flip-flop
using this JK flip-flop so as you can
see from the title it's a master slave
JK flip-flop ok so we are going to be
making a master slave setup using JK
flip-flop so the first step is to first
eliminate these feedback lines from the
first JK flip-flop so there are going to
be two flip-flops that is two JK
flip-flops being used in this assembly
and as the name suggests one is going to
be the master flip-flop and the next one
is going to be the slave flip-flop so
let's first remove these pink lines
which are the feedback lines of the
first JK flip-flop okay so we have
removed those feedback lines now the
next step is to add one more JK
flip-flop which is going to be acting as
a slave flip-flop so let's add that okay
so as you can see in the screen we have
added one more flip-flop which is also a
JK flip-flop and this one is the slave
flip-flop and now what we have to do is
we have to connect the out
or the first master flip-flop Q and Q
Bar as inputs as jnk for the slave
flip-flop okay
so let's connect that you can see this
blue line is connected to the yellow
line and over here so this is that
connection happening over here so this Q
and Q Bar becomes the intermediate
output from the master flip-flop which
is directly fed to the slave flip-flop
and you'll understand why we are doing
this because this exact scenario and
assembly is going to help us avoid that
erasing condition so okay this is step
number one now step number two is to add
the feedback again so we remove the
feedback of the first master flip-flop
rate so it has to have some feedback so
that that is going to come from the
slave flip-flop okay so let's add those
pink lines again so Q is going to be
connected to K of the master flip-flop
and Q Bar is going to be connected to G
of the master flip-flop so now the
feedback loop is and the only thing now
remaining is the clock so for master
flip-flop you can see that there is
clock available where but we have a
clock input for the slave flip-flop also
so here's where the catch is so the
master gets clocked directly however the
slave gets a inverted clock so what's an
inverted clock so the slave will get the
clock input from the same clock which is
ca key over here but it will get it in
an inverted way which means that it is
going to be passing to a not gate okay
so I hope you are getting this so this
is a not gate over here so what happens
is if this master flip-flop is going to
get one it will pass through this not
gate and it will become 0 so this clock
will be 0 and conversely if this is 0
then this is going to be 1 so this is
that catch over here and this is done
for a specific reason and we'll
understand that from the truth table and
then need also see the timeline chart of
the signals so that it will be more
clear how it is used to avoid that
racing condition but yeah this is the
complete structure of the master slave
flip-flop this is that circuit diagram
now we've completed it so let's move on
to the next part that is the truth table
okay so as you can see on the screen
here is a huge through table but don't
worry it's going to be very easy now
there are 16 different sub cases for
which we are going to be calculating the
intermediate output that is Q m and Q
Bar M so this qmn cube R M are the
individual output which are coming from
the first master flip-flop that's why
it's an orange you can see that that's
what we're going to be tracking over
here because that is needed to calculate
the next state because they are going to
be providing the input to the slave
flip-flop which we will be using to
calculate the next state which is QN
plus 1 and Q Bar n plus 1 okay now why
are there sixteen different combinations
basically there are four different cases
so this is case number one this is case
number two this is case number three and
this is case number four and these four
cases are corresponding to the very
ating inputs okay so we have JK as zero
for the first four cases then we have 0
1 we have 1 0 & 1 1 but the reason why
we have 4 different cases in each of
those single cases is because we are
assuming 0 1 as the previous state or
the current state one time and we are
assuming so this is the assumptions that
we have to make right we have to assume
the current state because we don't know
what exactly the current state is and
the current state is then provided as a
feedback to calculate the next state and
again we are assuming 0 1 0 & 2 times
because the clock is also changing two
times that is there are two different
clock signals one is going for the
master flip-flop and one is going for
the slave flip-flop so that is the
reason why there are four different sub
cases so there's going to be very quick
and easy don't worry that there are so
many different cases and the output is
gonna be different it's going to be very
much the same in all the cases so you'll
see that in a minute so before we
actually start off let's understand this
clock signals so as I mentioned the
clock is inverted for the slave right so
it goes through a not gate which is over
here so if clock off master is one clock
off sleeve is 0 now this circuit that
we've considered is a level triggered
circuit okay and it is a positive level
triggered circuit which means that
whenever the clock is positive which is
one one of the flip-flop is going to be
active and the other one is going to be
inactive and by inactive I mean it is
going to be in the latch state so we've
seen in the flip-flop of JK flip-flop
that if the clock is going to be 0 or if
it is low then it acts as our latch
right so same is the case over here
so for master if it is one clock is 0
which means that the slave flip-flop
this
flop is gonna be in the latch state
right so the QN plus 1 and Q Bar n plus
1 which is going to be coming out from
the slave flip-flop is going to be
exactly equal to the previous state
right which is latch state so if you see
the first case if clock off slave is 0 Q
n plus 1 and Q Bar n plus 1 is going to
be in the latch state so these two
values are going to be in the latch to
drive so similarly whenever the clock is
0 for slave it is gonna be in the latch
state and whenever the value of clock of
master is 0 the master is one of in the
last state right so without even
thinking about anything we can directly
fill out some of these blanks with latch
state so let me just fill that out okay
so there you go you can see that
whenever the clock of the respective
flip-flop is 0 the output is gonna be in
the latch state and latch state which
means the previous state so for this
latch state it means that the previous
state so QN and Q Bar n are the previous
values which has 0 and 1 and if it is
latched it again means it is 0 and 1
okay latch it is also known as previous
state or memory state okay so most of
the values we've already got filled out
now let's start off with the truth table
I will take the first case let's say a
clock of M that is clock of master is 1
which means our master is active let's
consider this one J and K we are
considering 0 and the previous case we
are considering Q n as 0 and Q Bar of n
as 0 so this we are considering to be 0
and Q Bar of n is as 1 the reason why we
are considering these values is because
of these pink lines which go as a feed
back to the very first master flip-flop
which you can see over here so that's
why we are making assumptions that the
previous state must have been 0 and 1 so
these values go so Q goes to the lower
NAND gate over here so this becomes 0
and this one goes to the upper NAND gate
which becomes 1 so now you can see the
output of the first two NAND gates of
the master flip-flop since there is zero
and zero Y or the output is going to be
1 and 1 so the output of these two NAND
gates that is the second level of NAND
gates in the forest master flip-flop is
to be determined based on the second
input rate because if one value to the
NAND gate is 1 the output is depending
on the next value so if it is 0 for the
output is going to be 1 and if it is
going to be 1 over here the output is
going to be 0 which means that we need
to know the value
of Q and Q Bar M right because these are
fed back over here so in a JK flip-flop
remember when the input was 0 and 1 the
output also was 0 and 1 right so that
was that reset state because Q Bar was 1
and Q was 0 so that is why we are
assuming Q and Q Bar
M s 0 and 1 so if we assume 0 & 1 over
here this 0 is going to be fed back over
here so 0 & 1 is gonna be 1 and this one
is going to be fed back over here and
then we get 0 so q MN q bar m are
assumed as 0 and 1 and then QN plus 1
and Q Bar n plus 1 is also going to be 0
and 1 because it is in the last state so
this was the first case and you can see
that we've assumed q MN q bar m as 0 and
1 because that's what the input would be
if you are getting or if you are
assuming Q and Q Bar over here as 0 & 1
right so let's see case number 2 what
happens over here so for case number 2
o'clock of M is 0 which means that
master is gonna be in the latitude so we
don't have to calculate Q m and Q Bar of
M because it is in the last state which
is 0 and 1 right that is the previous
state so directly we can assume qa0q bar
as 1 and now the clock of slave is gonna
be 1 right so that's over your so now
let's calculate the values so for the
lower angle it is 1 & 1 which means the
output is going to be 0 for the upper
NAND gate it is 0 & 1 which means the
output is gonna be 1 lower danged when
input is 0 the output is gonna be when
that sound angles work
this one is supplied over here when and
when output is going to be 0 so we got
QN plus 1 as 0 and Q Bar n plus 1 as 1
right so what did we get over here 0 1
so notice that this 0 1 is now coming
from the slave flip-flops output so
master flip-flops output was coming 0
and 1 in the first case and once the
clock was switched to 0 and 1 that same
output is coming outside from the slave
flip-flop similarly the second case is
also going to be the same so in this
case we are going to be assuming 1 0 and
the output is what are we coming as 1 0
now you can go ahead and substitute
these values and check it out yourself
but if you do that it will take a lot of
time so now just observe all these four
cases when the input to JK is 0 0 in all
the four key
is whatever we've assumed zero one is
what we are getting as the output right
in the first case we are assuming zero
and one has the previous state and the
next state is in the latched which means
it is zero and one and even when the
clock is switched and when we are
assuming zero and when the output is
also zero and one again for the third
and fourth case it is the same one zero
one zero one zero and one zero so this
entire four cases was the no change case
of the JK flip-flop right so if you see
in the JK flip-flop also when the input
is zero and zero and clock is one now
output is no change so these four sub
cases represent that no change case
similarly for the next four cases it is
gonna be reset
that is it is going to be zero one and
the output over here is also going to be
0 1 then it is going to be 1 0 and 1 0
over here so these four cases is going
to be reset and during reset J is zero
but K is 1 ok for the next 4 it is going
to be set wherein J is 1 but K is 0 so
again 0 1 is going to be transferred
over here 0 1 if we assume 1 0 not 1 0
is going to come out over here and now
lastly this fourth state is what is most
important so we are going to be taking a
look at this state in deep and I did not
cover reset and set because it is just
as the first one whatever output is
coming at the intermediate level is
being just transferred but over your
these four are the toggle cases which
happens in master slave JK flip-flop so
that's what we are going to be taking a
look at in proper detail because your GN
k is 1 and 1 and the previous is or the
current state what we are assuming is 0
and 1 however at the output over here we
are going to get 1 0 which means that it
is going to be toppled so let's see how
that works ok so let's take a look at
the first case so your clock is 1 right
clock of master is 1 o'clock of sleeve
is 0 which means that slave is gonna be
in the latch state J and K are both 1
and 1 right and we are assuming previous
state as 0 and 1 so we are assuming Q as
0 and Q Bar as 1
so let's transfer this Q 0 if the lower
NAND gate over here because it is as
coming as a feedback and this one goes
over here so 3 of them are 1 which means
the output is going to be 0 and one of
them is 0 at the lower NAND gate which
means our
is gonna be one now again for this NAND
gate one of the input is 0 which means
output is going to be 1 and this one is
now transferred over here so 1 & 1
output is going to be 0 so what did we
get as intermediate values just take a
note of them Q is 1 and Q Bar is 0 so
initially what we assumed is 0 & 1 but
the intermediate Q and Q Bar is coming
as 1 & 0 so let me just write down 1 & 0
over here now when we move from first to
second case here the clock is just
changed everything else is the same
so now master is going to be in the
latch state so we are not calculating
anything for the master we are
calculating everything for the slave now
so only one change that is the clock of
the slave is going to be 1 and clock on
the master is going to be 0 so now let's
calculate with these values that we've
got in the intermediate state so Q is 1
and clock is 1 which means the output is
going to be 0 for your and for the lower
NAND gate one of them is 0 so the output
is going to be one for the upper NAND
gate of the slave flip-flop one of the
input is 0 output is going to be 1 so we
got QN plus 1 as 1 and this one is
transferred back over here so 1 and 1
the output is going to be 0 so we got 1
and 0 so now notice that initially we
assumed zero 1 as the previous state but
the next state that we are getting is 1
0 which means that we are getting a
toggling kind of situation right
similarly for the last two cases also if
we assume 1 0 the intermediate values
which we will get is 0 1 and the next
state is also going to be 0 1 so you can
put these values in the circuit if you
have and check it out so here this was
about the toggle state that I wanted to
show you in the truth table but let's
get into more detail and let's see the
toggle state in the actual action that
is on the graph on the timeline chart
wherein the signals are being depicted
so let me just turn that on okay so as
you can see on the screen I have the
chart and now what we are going to plot
is for these four cases or we are just
going to be tracking the Q actually the
Q that is QN plus 1 so that signal we
are going to track so let's say let's
take the first case clock of M is 1 and
clock of s is 0 so from the chart you
can see that clock of M is 1 block of s
is 0 J and K are both 1 so it's going to
be 1/2 out or
the four cases sue J and K is one over
here the previous value of Q so we are
tracking Q we are not tacking to but
even if we track one of them is more
than enough because it's just going to
be complement of each other but we are
tracking Q so you can see the previous
state was zero so we will be starting
from this point over here so let me just
mark it in move and what you can see is
for the next state also it is in the
last state right which means that Q is
always going to be zero for this entire
cycle till clock off master is 1 and
slave is 0 which means that QN plus 1 is
going to be 0 for this duration right
because this is the deviation will clock
off master is 1 and clock of slave is 0
but now what happens is clock of master
becomes 0 so we are taking a look at the
next case
krokov master becomes 0 and clock of
slave becomes 1 so now what happens is
you can see that initial state was 0 of
Q which is what we have here but the
next state you can see in the same case
is Q becomes 1 so QN plus 1 becomes 1
right so now it's gonna stay 1 till this
entire clock of master is 0 and clock of
slave is 1 okay so from year to year it
is gonna stay 1
now let's move on to the third case in
the third case the clock again flips so
clock of master becomes 1 and clock of
slave becomes 0 however you can see that
QN is 1 in the previous state so we are
at this point and the next state is also
in the last state which means that QN
plus 1 is also 1 so it's continuing to
stay at a higher level right so we have
reached over here now let's see the next
case that is the fourth case again the
clock is flipped over your clock of
Master goes 0 so we are over your clock
of Master go 0 and clock of slave
becomes 1 j NK is always 1 so that's why
these are always high you can see the
yellow lines but now if you see the
previous tito is 1 so previous state of
QN is 1 over here you can see that so we
are at the last state right so QN is 1
but the next state is Q n becomes 0 so
this is the fourth state and this is
gonna happen every time these four
states are happening in cycle so after
this the clock will again become higher
rate for the master and then
is how the graph will look like I don't
even have to explain to you this is how
the graph will look like when we repeat
all these for in this order okay so if
you observe QN plus 1 that is this next
step that we are getting over here it is
always going to be 0 then 1 then 0 then
1 then 0 then 1 right you can see 0 1 0
1 so this is known as toggle okay so
this is that toggling step that I was
talking about and here you can see that
there is no race condition which means
that using master/slave JK flip flop
assembly you are avoiding that
uncontrolled racing condition but you
are achieving the toggle state and this
toggling is happening for one complete
cycle which means that for this complete
cycle so this is one complete cycle rate
so clock goes from 0 to 1 so this is
that complete cycle again this is the
next complete cycle and this is the next
complete cycle or if you start from over
here then this is one cycle this is
another cycle and the length of QN being
in one state is also the same rate so
that's why I am saying that the output
stays high for one complete cycle then
goes low for the next complete cycle so
it is controlled and that's why it is
known as toggle state so yeah that's it
for this video guys I hope you
understood the complete concept of
master/slave JK flip-flop assembly
wherein there are two JK flip-flops
connected in this fashion which you can
see on the screen and then we also saw
the truth table and we discussed the
last case in detail because that is the
case where the actual toggling was
happening and the previous three cases
are similar to the JK flip-flop but in
the last case we saw that the race
condition was avoided and we got a
proper control toggling stood by looking
at the time line chart so that's it for
this video guys I hope you understood
this concept if you liked this video
please give it a thumbs up and let me
know in the comments that you liked this
if you have any doubts you can always
put them in the comment section so hope
you enjoyed this I'll talk to you guys
in the next video tutorial peace