Transistor Biasing & Stabilization | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

NEED FOR TRANSISTOR BIASING:

If the o/p signal must be a faithful reproduction of the i/p signal, then transistor must be operated in active region. That means an operating point has to be established in this region . To establish an operating point (proper values of collector current I_C and collector to emitter voltage V_CE) appropriate supply voltages and resistances must be suitably chosen in the circuit. This process of selecting proper supply voltages and resistance for obtaining desired operating point or Q point is called as biasing and the circuit used for transistor biasing is called as biasing circuit.

There are four conditions to be met by a transistor so that it acts as a faithful amplifier:

1. Emitter base junction must be forward biased (V_BE=0.7Vfor Si, 0.2V for Ge) and collector base junction must be reverse biased for all levels of i/p signal.
2. V_ce voltage  should not fall below V_CE (sat) (0.3V for Si, 0.1V for Ge) for any part of the i/p signal. For V_CE less than V_CE (sat) the collector base junction is not probably reverse biased.
3. The value of the signal I_c when no signal is applied should be at least equal to the max. collector current due to signal alone.
4. Max. rating of the transistor I_c(max), V_CE (max) and P_D(max) should not be exceeded at any value of i/p signal.

Consider fig1. If operating point is selected at A, A represents a condition when no bias is applied to the transistor i.e, I_C=0, V_CE =0. It does not satisfy the above stated conditions necessary for faithful amplification.

Point C is too close to P_D(max) curve of the transistor. Therefore  the o/p voltage swing in the positive direction is limited.

Point B is located in the middle of active region. It will allow both positive and negative  half cycles in the o/p signal. It also provides linear gain and larger possible o/p voltages and currents.

Hence operating point for a transistor amplifier is selected to be in the middle of active region.

DC LOAD LINE:

Referring to the biasing circuit of fig 4.2a, the values of V_CC and R_C are fixed and I_C and V_CE are dependent on R_B.

Applying Kirchhoff’s voltage law to the collector circuit in fig. 4.2a, we get  

                                       V_CC= I_CR_C + V_ce
 

The straight line represented by AB in fig4.2b is called the dc load line. The coordinates of the end point A are obtained by substituting V_CE =0 in the above equation. Then 

I_CC = V_CC/R_C  Therefore The coordinates of A are  V_CE =0 and I_CC = V_CC/R_C.

The coordinates of B are obtained by substituting I_C=0 in the above equation. Then Vce = Vcc. Therefore the coordinates of B are V_CE =Vcc and I_C=0. Thus the dc load line AB can be drawn if the values of R_C and V_CC are known.

As shown in the fig4.2b, the optimum POINT IS LOCATED AT THE MID POINT OF THE MIDWAY BETWEEN A AND B. In order to get faithful amplification, the Q point must be well within the active region of the transistor.

Even though the Q point is fixed properly, it is very important to ensure that the operating point remains stable where it is originally fixed. If the Q point shifts nearer to either A or B, the output voltage and current get clipped, thereby distorting the o/p signal.

In practice, the Q-point tends to shift its position due to any or all of the following three main factors.

1. Reverse saturation current, Ico, which doubles for every 10^oC raise in temperature
2. Base emitter Voltage ,VBE, which decreases by 2.5 mV per ^oC
3. Transistor current gain, h_FE or β which increases with temperature.  

If base current I_B is kept constant since I_B is approximately equal to Vcc/R_B. If the transistor is replaced by another one of the same type, one cannot ensure that the new transistor will have identical parameters as that of the first one. Parameters such as β vary over a range. This results in the variation of collector current I_C for a given I_B. Hence , in the o/p characteristics, the spacing between the curves might increase or decrease which leads to the shifting of the Q-point to a location which might be completely unsatisfactory.

AC LOAD LINE:

After drawing the dc load line, the operating point Q is properly located at the center of the dc load line. This operating point is chosen under zero input signal condition of the circuit. Hence the ac load line should also pass through the operating point Q. The effective ac load resistance R_ac, is a parallel combination of R_C and R_L i.e. R_ac = R_L || R_C. So the slope of the ac load line CQD will be . To draw the ac load line, two end points, i.e. V_CE(max) and I_C(max)  when the signal is applied are required.

V_CE(max)=V_CEQ+I_CQR_ac, which locates point D on the Vce axis.

  which locates the point C  on the I_C axis.

By joining points C and D, ac load line CD is constructed. As R_C > R_ac, The dc load line is less steep than ac load line.

STABILITY FACTOR (S):

            The rise of temperature results in increase in the value of transistor gain β and the leakage current I_CO. So, I_C also increases which results in a shift in operating point. Therefore, The biasing network should be provided with thermal stability. Maintenance of the operating point is specified by S, which indicates the degree of change in operating point due to change in temperature.

The extent to which I_C is stabilized with varying temperature is measured by a stability factor S.

       For CE configuration

Differentiate the above equation w.r.t I_C , We get

S should be small to have better thermal stability.

Stability factor S’ and S’’:

S’ is defined as the rate of change of   I_C with V_BE, keeping I_C and V_BE constant.

S’’ is defined as the rate of change of   I_C with β, keeping I_CO and V_BE constant.