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Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q1: In the circuit, the present value of Z is 1 . Neglecting the delay in the combinatorial circuit, the values of S and Z, respectively, after the application of the clock will be (2024)
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) S=0,Z=0S = 0, Z = 0
(b) S=0,Z=1S = 0, Z = 1
(c) S = 1, Z = 0
(d) S=1,Z=1S = 1, Z = 1
Ans:
(c)
Sol: Based on this trick
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q2: Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is (2023)
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 4
(b) 8
(c) 16
(d) 32
Ans:
(b)
Sol: Redraw the circuit :
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)From circuit :
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)∴ ABCD = (1000)2 = (8)10

Q3: The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)  (2022)
(a) 15.5
(b) 20.4
(c) 12.5
(d) 8.6
Ans: 
(c)
Sol: Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)

Q4: A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer) (2022)
(a) 5
(b) 10
(c) 50
(d) 25
Ans:
(b)
Sol: Overall MOD = 2 x 5 = 10

Q5: A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency  fCLK is ___________ MHz. (Round off to 2 decimal places.) (2021)
(a) 4.12
(b) 2.05
(c) 6.08
(d) 3.25
Ans:
(b)
Sol:
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)y = 1 for 24 m sec
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Total number of states for which y = 1 is 216 − 214
Time is (216− 214)T = 24msec
f = 1/T = 2.05 MHz

Q6: A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1, 0, 1) and input data (1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 0):
what is the output of this detector? (2020)
(a) 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0
(b) 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0
(c) 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0
(d) 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0
Ans:
(b)
Sol: Given overlapping sequence input data =11010011010110
It will give output 1 when 101 is detected.
110−0
101−1
010−0
100−0
001−0
011−0
110−0
101−1
010−0
101−1
011−0
110−0
So, output = 010000010100

Q7: Which one of the following statements is true about the digital circuit shown in the figure (2018)
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) It can be used for dividing the input frequency by 3.
(b) It can be used for dividing the input frequency by 5.
(c) It can be used for dividing the input frequency by 7.
(d) It cannot be reliably used as a frequency divider due to disjoint internal cycles.
Ans: 
(b)
Sol: Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)So, frequency will be divided by 5.

Q8: For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions QAQBQC = QA′QB′QC′ = 100
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)The minimum number of clock cycles after which the output Z would again become zero is ________ (SET-2 (2017))
(a) 4
(b) 5
(c) 6
(d) 7
Ans:
(c)
Sol:
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)The output Z will again become zero after 6th clock cycle.

Q9: The current state QAQB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is (SET-1(2016))
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 00
(b) 01
(c) 11
(d) 10
Ans:
(c)
Sol: From the figure we get
JA = KA = 1
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)So, next state will be 11.

Q10: In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q1Q0 = 00. The state (Q1Q0), immediately after the 333rd clock pulse is (SET-2  (2015))
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 00
(b) 01
(c) 10
(d) 11
Ans:
(b)
Sol: From the circuit, we can find out that
J0 = Q1′, K0 = Q1
J1 = Q0, K1 = Q0
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)So state diagram is
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)at every 4th clock, the system is at 00
So, at 332 it will be at 00
So, at 333 clock it will be at 01.

Q11: The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q2Q1Q= 000. This state Q2Q1Q= 000 will repeat after _______ number of cycles of the clock CLK (SET-1(2015))
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 4
(b) 5
(c) 6
(d) 7
Ans:
(c)
Sol: JK flip-flop1 and 2 from a syncgronous sequential circuits and they are synchronized with the output of 0th JK flip-flop.
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Number of cycles = 3 i.e. equal to 6 clock cycles.

Q12: A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don't care condition, and Q is the output representing the state. The logic gate represented by the state diagram is (SET-3 (2014))
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) XOR
(b) OR
(c) AND
(d) NAND
Ans: 
(d)
Sol: Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)If any one of the input is zero, output is 1 and for both inputs as '1' , output is '0', which represents the NAND gate.

Q13: A JK flip flop can be implemented by T flip-flops. Identify the correct implementation. (SET-2 (2014))
(a) Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(b) Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(c) Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(d) Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Ans:
(b)
Sol: To obtain a JK flip-flop from a T flip-flop, we first constuct the characteristic table of JK flip-flop, and then obtain the excitation values for the T flip-flop as shown below
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Now, assuming T to be an output, we solve it in terms of J, K, Qn inputs. This gives the defination of the logic to be applied on the T input.
Also, observing the given options, we solve for T using a maxterms map instead of using a minterms map, as shown below
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)The circuit corresponding to this expression is given in option (B).

Q14: A cascade of three identical modulo-5 counters has an overall modulus of  (SET-1 (2014))
(a) 5
(b) 25
(c) 125
(d) 625
Ans:
(c)
Sol: Overall modulus = 5 x 5 x 5 = 125

Q15: The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the frequency of the output waveform Q in kHz is  (2013)
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 0.25
(b) 0.5
(c) 1
(d) 2
Ans:
(b)
Sol: Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)∵ X = 1 = T ⇒ Q always toggle whenever clock triggers.
Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)

The document Previous Year Questions- Sequential Logic Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) is a part of the Electrical Engineering (EE) Course Analog and Digital Electronics.
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