Field Effect Transistor | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Introduction

• The Field effect transistor abbreviated as FET , is an another semiconductor device like a BJT  which can be used as an amplifier or a switch.
  
• The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a current controlled device. Unlike BJT a FET requires virtually no input current.
• This gives it an extremely high input resistance, which is its most important advantage over a bipolar transistor.
• FET is also a three-terminal device, labelled  as source, drain and gate.
  
• The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the counter part of the base.
• The material that connects the source to drain is referred to as the channel.
• FET operation depends only on the flow of majority carriers; therefore they are called uni polar devices. BJT operation depends on both minority and majority carriers.
  
  Question for Field Effect Transistor

  Try yourself:Which one is a unipolar device?

  • A.

    FET
  • B.

    BJT
  • C.

    Both a and b
  • D.

    None of the above

  Explanation

  Field Effect Transistor is a unipolar device.

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• As FET has conduction through only majority carriers it is less noisy than BJT.
• FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less space than BJTs.
  
• FET amplifiers have low gain bandwidth product due to the junction capacitive effects and produce more signal distortion except for small signal operation.
• The performance of FET is relatively unaffected by ambient temperature changes. As it has a negative temperature coefficient at high current levels, it prevents the FET from thermal breakdown. The BJT has a positive temperature coefficient at high current levels which leads to thermal breakdown.

Classification of FET

There are two major categories of field effect transistors:

1. Junction Field Effect Transistors (JFET)
2. MOSFETs

1. Depletion MOSFETs
2. Enhancement MOSFETs.

Construction & Operation of N- Channel FET

(i) Construction of N- Channel JFET

• A piece of N- type material, referred to as channel has two smaller pieces of P-type material attached to its sides, forming PN Junctions.
• The  channel ends are designated as the drain and source . And the two pieces of P-type material are connected together and their terminal is called the gate.
• Since this channel is in the N-type bar, the FET is known as N-channel JFET.

(ii) Operation of N- Channel JFET

• The overall operation of the JFET is based on varying the width of the channel to control the drain current.
• A piece of N-type material referred to as the channel, has two smaller pieces of P-type material attached to its sites, forming PN-Junctions. 
• The channel’s ends are designated the drain and the source. And the two pieces of P-type material are connected together and their terminal is called the gate. 
• With the gate terminal not connected and the potential applied positive at the drain and negative at the source, a drain current I_d flows. 
• When the gate is biased negative with respect to the source, the PN junctions are reverse biased and depletion regions are formed. The channel is more lightly doped than the P-type gate blocks, so the depletion regions penetrate deeply into the channel. 
• Since depletion region is a region with less no. of charge carriers so it behaves as an insulator. The result is that the channel is narrowed. Its resistance is increased, and I_d is reduced. 
• When the negative gate bias voltage is further increased, the depletion regions meet at the center and Id is cut off completely.

There are two ways to control the channel width

1. By varying the value of V_gs
2. By Varying the value of V_ds  holding V_gs constant

1. By Varying the Value of V_gs

• We can vary the width of the channel and in turn vary the amount of drain current. This can be done by varying the value of Vgs. This point is illustrated in the fig  below.
• Here we are dealing with N-channel FET. So channel is of N-type and gate is of P-type that constitutes a PN junction. This PN junction is always reverse biased in JFET operation.
• The reverse bias is applied by a battery voltage Vgs connected between the gate and the source terminal i.e positive terminal of the battery is connected to the source and negative terminal to gate.

• When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving immobile ions on the N and P sides , the region containing these immobile ions  is known as depletion region.
• If both P and N regions are heavily doped then the depletion region extends symmetrically on both sides.
• But in N-channel FET P region is heavily doped than N-type thus depletion region extends more in N region than P region.
• So when no V_ds is applied the depletion region is symmetrical and the conductivity becomes zero. Since there are no mobile carriers in the junction.
• As the reverse bias voltage increases the thickness of the depletion region also increases.  i.e. the effective channel width decreases .
• By varying the value of V_gs we can vary the width of the channel.

2. Varying the value of V_ds  holding V_gs constant

n-channel JFET with gate open & V_DD applied between drain and source

• When no voltage is applied to the gate i.e. V_gs=0 , V_ds is applied between source and drain the electrons will flow from source to drain through the channel constituting drain current I_d .
• With V_gs= 0 for I_d= 0, the channel between the gate junctions is entirely open. In response to a small applied voltage V_ds , the entire bar acts as a simple semi-conductor resistor and the current I_d increases linearly with V_ds .
• The channel resistances are represented as r_d and r_s as shown in the fig above.
• This increasing drain current I_d produces a voltage drop across r_d which reverse biases the gate to source junction,(r_d> r_s). Thus the depletion region is formed which is not symmetrical .
• The depletion region developed penetrates deeper into the channel near drain and less towards source because V_rd >> V_rs. So reverse bias is higher near drain than at source.
• As a result, growing depletion region reduces the effective width of the channel. Eventually a voltage V_ds is reached at which the channel is pinched off. This is the voltage where the current I_d begins to level off and approach a constant value.
•  So, by varying the value of V_ds we can vary the width of the channel holding V_gs constant.

When both V_gs and V_ds is applied

Experimental setup to plot JFET characteristics

• It is of course in principle not possible for the channel to close completely and thereby reduce the current I_d to zero, if such indeed, could be the case the gate voltage Vgs is applied in the direction to provide additional reverse bias.

• When voltage is applied between the drain and source with a battery V_dd, the electrons flow from source to drain through the narrow channel existing between the depletion regions. This constitutes the drain current I_d, its conventional direction is from drain to source.
• The value of drain current is maximum when no external voltage is applied between gate and source and is designated by I_dss.
• When V_gs is increased beyond zero the depletion regions are widened. This reduces the effective width of the channel and therefore controls the flow of drain current through the channel.
• When V_gs is further increased a stage is reached at which to depletion regions touch each other that means the entire channel is closed with depletion region. This reduces the drain current to zero.