Biasing FET - Analog and Digital Electronics - Electrical Engineering (EE)

BIASING FET:-

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stably in the central portion of the pinch-off (or saturation) region. The Q-point must be reasonably independent of device parameter variations (for example, variations in Idss and Vp) and of ambient temperature. Selecting an appropriate gate-to-source voltage V_GS and drain current I_D so that the device operates at the desired Q-point is called biasing.

JFET biasing circuits are similar in purpose to BJT biasing circuits; the main difference is the device physics (a reverse-biased PN junction controls the channel in a JFET, whereas base current controls a BJT). The common biasing approaches for JFETs are:

1. Self bias
2. Voltage-divider bias

Self bias

Self bias (also called source-feedback bias) is the most common biasing method for JFETs. It uses a resistor in the source lead that develops a voltage from the source current; this voltage makes the gate-to-source junction reverse biased for an N-channel JFET (or forward biased in the required polarity for a P-channel device) and thus establishes the operating point.

Important features of the self bias arrangement are:

• The gate resistor R_G is typically large and, because the gate current is negligible, the voltage drop across R_G is essentially zero for DC; therefore the gate is held at (or very near) ground potential in common-source grounded-gate arrangements.
• All source current passes through the source resistor R_S; hence the source becomes positive with respect to ground by an amount V_S = I_SR_S. For negligible gate current, I_S = I_D.
• As the drain current increases, the source voltage increases and thus V_GS becomes more negative (for an N-channel JFET), which reduces the drain current; this negative feedback tends to stabilise the operating point against device or temperature changes.

For DC analysis the coupling capacitors are open circuits and the gate resistor may be treated as an open circuit for DC insofar as gate current is negligible. For the N-channel self-biased JFET shown above, the DC relations are:

I_S = I_D

V_S = I_D · R_S

V_GS = V_G - V_S = 0 - I_DR_S = - I_DR_S

DC relation between I_D and V_GS

The JFET transfer (Shockley) equation relates I_D to V_GS in the pinch-off/saturation region:

I_D = I_DSS [1 - (V_GS / V_P)]²

Since for self bias V_GS = - I_D R_S, substituting into the Shockley equation gives an equation in I_D only. This implicit equation determines the DC operating current for a chosen R_S and device parameters I_DSS and V_P.

Drawing the self-bias (load) line

Graphically, the self-bias operating point is found by plotting the device transfer curve (I_D versus V_GS) and the self-bias line given by V_GS = - I_D R_S. The intersection is the Q-point.

Procedure to draw the self-bias line (example):

• Choose two convenient points on the straight line defined by V_GS= -I_DR_S. A convenient pair is I_D=0 and I_D=I_DSS.
• For I_D=0, V_GS=0, giving the point (0, 0).
• For I_D=I_DSS, V_GS= - I_DSS R_S, giving the second point.

Example from a typical device: I_DSS = 6 mA and gate-cutoff V_P = -3 V. If R_S = 500 Ω, then:

For I_D = 0: V_GS = 0 × 500 Ω = 0 V (point (0, 0)).

For I_D = I_DSS = 6 mA: V_GS = -6 mA × 500 Ω = -3 V (point (6 mA, -3 V)).

Plotting these two points yields the straight self-bias line; its intersection with the device transfer curve determines the Q-point. In the example the intersection gives an operating current slightly greater than 2 mA and a V_GS slightly greater than -1 V. If R_S is increased, the self-bias line rotates so that the Q-point moves down the transfer curve (smaller I_D); if R_S is decreased, the Q-point moves up (larger I_D).

Voltage-divider bias

Voltage-divider bias uses a resistor pair to set the gate voltage and provides improved stability of the gate potential compared with a simple self-bias when gate leakage can be significant or when a specific gate voltage is required.

In the voltage-divider arrangement, the gate voltage V_G is determined by the divider resistors R₁ and R₂ according to the standard voltage-divider formula:

V_G = V_DD · R₂ / (R₁ + R₂)

For DC analysis, coupling capacitors are open circuits and small AC components are ignored. Assuming negligible gate current, V_G is fixed by the divider and the source voltage is V_S = I_D R_S, so the gate-to-source voltage is:

V_GS = V_G - V_S = V_G - I_D R_S

Applying Kirchhoff's voltage law around the drain circuit gives:

V_DS + I_D R_D + V_S - V_DD = 0

Hence

V_DS = V_DD - I_D R_D - I_D R_S = V_DD - I_D (R_D + R_S)

The Q-point for a JFET with voltage-divider bias is given by the Shockley relation together with the gate voltage determined by the divider. Thus:

I_D(Q) = I_DSS [1 - V_GS / V_P ]²

V_DS(Q) = V_DD - I_D(Q) ( R_D + R_S )

Design comments for voltage-divider bias:

• Choose R₁ and R₂ so that V_G is at the desired value for the intended Q-point. Then select R_S (and R_D) to place the Q-point at a suitable drain current and drain-to-source voltage.
• The divider current should be large enough compared to any gate leakage so that the gate voltage is not significantly changed by gate current. In practice the divider current is made much larger than the gate leakage current; for JFETs the gate leakage is usually very small, but the divider must still be chosen to give adequate stability while not wasting excessive power.
• Voltage-divider bias gives better DC stability than simple fixed bias and is commonly used where a relatively constant gate potential is required.

Comparison of MOSFET with JFET

1. In enhancement and depletion MOSFETs, the transverse electric field induced across an insulating gate oxide controls the conductivity of the channel.
2. In a JFET, the transverse electric field across a reverse-biased PN junction controls the conductivity of the channel.
3. The gate leakage current in a MOSFET is typically of the order of 10^-12 A, so the input resistance of a MOSFET is very high (of the order of 10¹⁰ to 10¹⁵ Ω). The gate leakage current of a JFET is larger (typically of the order of 10^-9 A) and its input resistance is of the order of 10⁸ Ω.
4. The output characteristics of JFETs are generally flatter than those of MOSFETs; consequently the small-signal drain resistance (r_o) of a JFET can be higher than that of a MOSFET. Typical JFET drain resistances range from about 0.1 to 1 MΩ while MOSFETs often show lower values (for discrete power or small-signal MOSFETs typical drain resistances are lower, e.g. 1 to 50 kΩ, depending on device and operating region).
5. JFETs are normally depletion-mode devices only (they conduct at zero gate bias and the channel is pinched off by reverse gate bias). MOSFETs exist in both depletion and enhancement types; enhancement MOSFETs require a gate bias to induce a conducting channel.
6. MOSFETs are generally easier to fabricate in modern CMOS processes and allow very high levels of integration.
7. CMOS digital circuits (which use MOSFETs) can be designed for very low static power dissipation and very low supply voltage/current requirements, making them well suited for portable systems.

Summary: Biasing a FET (JFET or MOSFET) establishes a stable DC operating point that allows linear amplification. Self bias uses source feedback to provide negative DC feedback and simple stabilisation; voltage-divider bias fixes the gate potential more rigidly and is used when a precise gate voltage is desired. Choice of biasing affects stability, quiescent dissipation and sensitivity to device parameter variations; appropriate calculation and graphical methods (transfer curve and bias line) are used to determine the Q-point.