Multi Bit Multiplexers & Addressing | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Multi-Bit Multiplexers

A multiplexer (often abbreviated mux) is a digital switch that selects one of several input signals and forwards the selected input to a single output line. Multiplexing is used wherever a number of signals or logic states must share a single communication channel - for example, on a wire, a bus inside a computer, or a radio/telephone channel. Multiplexing and de-multiplexing ranges from very simple circuits to complex systems depending on distance, required speed, and the number of signals to be carried.

Basic principle

A basic single-bit n-to-1 multiplexer has n data inputs, one output, and log2(n) address lines (control lines) that determine which input is connected to the output. For example, a 4-to-1 multiplexer has four data inputs, one output and two address lines. The address lines select one of the four inputs to appear at the output.

4-to-1 multiplexer - explanation and Boolean form

The 4-to-1 single-bit multiplexer selects one input from D0, D1, D2, D3 using two address lines A1 (most significant bit, MSB) and A0 (least significant bit, LSB). When only one input should be enabled at a time, the selected data passes to the output Y while other inputs are disabled.

Boolean expression for the output Y of a 4-to-1 mux can be written as:

Y = A1̄ A0̄ D0 + A1̄ A0 D1 + A1 A0̄ D2 + A1 A0 D3

Here A1̄ denotes the complement (NOT) of A1. This expression shows that the selected data input is gated through by the decoded address combination.

Implementations using basic gates

A 4-to-1 multiplexer can be implemented using logic gates and simple decoders or with a set of NAND/NOR gates arranged so that only the selected data input is enabled. For example, a design may use four 3-input NAND gates where two inputs of each NAND are driven by the address lines (with appropriate inversion) so that only one NAND receives two logic 1s on its address inputs. The third input of each NAND gate is the corresponding data input. The outputs of these gates are combined (for example by another NAND or OR stage depending on active level) to produce the final output.

When address lines are both 0, the inverters on those lines produce the required high inputs to enable the NAND gate associated with address 00. When A0 = 1 and A1 = 0, the NAND gate for address 01 is enabled, and so on. This method is an example of using simple decoding of address lines to enable the required data gate.

Addressing

Addressing is the method of using binary codes on control lines to select which data input is connected to the output. For an n-to-1 multiplexer the number of address lines required is m = log2(n). The address lines provide 2m distinct binary combinations, each combination enabling one of the n inputs.

For multi-bit data (words) the same address lines are shared by a group of single-bit multiplexers, one multiplexer per data bit. For example, to pass a 4-bit word chosen from four 4-bit words, use four 4-to-1 single-bit multiplexers (one per bit) and share the two address lines across them. Thus the address/control lines remain only two, while four parallel data wires carry the selected 4-bit word.

Address decoding and enables

Address decoding is often implemented with a small decoder circuit that produces one active enable line for the selected input. The enable line is used together with the data input to gate the data through to the output. Decoders may produce active-high or active-low enables; the gate network must be arranged consistently with the enable polarity. Commercial multiplexer ICs often include an enable pin to turn the whole device on or off.

Multi-bit multiplexers and bus multiplexing

A multi-bit multiplexer means either a multiplexer that takes multi-bit inputs internally (ICs providing parallel channels) or a set of identical single-bit muxes arranged side-by-side to form a word-wide mux. When multiplexing a parallel data bus, the address lines are common for all bits and the data lines are parallel lines for each bit of the word. This is the usual method inside CPUs and memory systems where several data words must be selected onto a single shared bus.

Expanding multiplexers for larger sizes

To build larger multiplexers from smaller ones, you can cascade or combine chips. For instance, two 4-to-1 multiplexers feeding a 2-to-1 multiplexer on their outputs can produce an 8-to-1 multiplexer, with three address lines where the MSB selects which 4-to-1 block to use and the lower two bits select the input inside that block. Expansion requires careful handling of enable signals and timing so that there are no bus contention or transient glitches.

Tri-state outputs and bus sharing

When several outputs can be connected to a common bus, outputs are often implemented as tri-state drivers. Each multiplexer output can be placed in a high-impedance state except for the selected device, preventing contention on the bus. Many multiplexer ICs provide tri-state outputs or an output enable pin for this reason.

Practical considerations

• Propagation delay: Multiplexers add delay from input to output; cascaded MUXes increase total delay. Designs must meet timing constraints of the system.
• Fan-out and loading: Outputs driving many inputs or a shared bus may require buffering.
• Glitches: During address transitions some implementations briefly connect two inputs; careful timing or glitch-free designs (using latches or synchronised address changes) are used in sensitive systems.
• Active level: Check whether the device uses active-high or active-low enables and whether outputs are inverted.
• Power and speed: Different IC families (HC, HCT, TTL, CMOS variants) differ in power consumption and maximum switching rate.

Applications

• Data selection and routing inside CPUs and digital systems.
• Bus arbitration and sharing multiple peripherals on a common bus.
• Time-division multiplexing for serial transmission of parallel data.
• Signal routing in measurement systems, data acquisition and instrumentation.
• Address-based selection of memory or I/O resources in microprocessor systems.

Multiplexer IC datasheets

There are many commercially available multiplexer ICs with a variety of features such as multiple channels, tri-state outputs, separate enables and complementary outputs. The list below names a few commonly used devices and their typical function; follow the manufacturer datasheet for electrical characteristics and pin details.

• 74HC151 - 8-to-1 single-bit multiplexer (8 data inputs, 3 address inputs). Useful when selecting one of eight signals to a single output. See the manufacturer datasheet for logic levels, propagation delay and enable polarity.

• 74HC153 - Dual 4-to-1 multiplexer. It contains two independent 4-to-1 multiplexers in one package, often with separate enable pins for each channel.

• 74HC257 - Quad 2-input multiplexer. Four independent 2-to-1 mux channels in one IC, typically used to multiplex four-bit buses or nibble-wide data paths.

• 74HC352 - Dual 4-to-1 multiplexer (two separate 4-to-1 channels per package). Useful for word-wide selection when two 4-to-1 channels are required.

Always consult the specific datasheet for supply voltage range, input/output voltage thresholds, propagation delay, power dissipation, and recommended operating conditions before using a device in a design.

Summary. A multiplexer selects one of several inputs under control of binary address lines. Multi-bit data is handled by parallel single-bit multiplexers sharing the address lines. Practical designs must consider decoding, enables, tri-state outputs, propagation delay and bus contention. Standard IC families (74HC series and similar) provide ready-made muxes that simplify implementation in digital systems.