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All questions of Control Unit for Computer Science Engineering (CSE) Exam
Which of the following is not involved in a memory write operation?- a)MAR
- b)PC
- c)MDR
- d)data bus
Correct answer is option 'B'. Can you explain this answer?
Which of the following is not involved in a memory write operation?
a)
MAR
b)
PC
c)
MDR
d)
data bus
|
Ravi Singh answered |
Program counter register used to read the value or instruction not in write operation. For write operation MAR, IR and MDR registers are used.
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.- a)22
- b)23
- c)24
- d)25
Correct answer is option 'B'. Can you explain this answer?
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.
1. Next Address field of 7 Bits
2. ALU Function field selecting 1 out of 13 ALU Function.
3. Register-in field selecting 1 out of 13 ALU Function.
4. Register-out field selecting 1 out of 8 registers.
5. Shifter field selecting no shift, right shift or left shift.
6. Auxiliary control field of 4 bits.
a)
22
b)
23
c)
24
d)
25
|
Shraddha Iyer answered |
Next Address Field = 7 Bits
ALU Function Field is of 4 Bits (to select possible 1 of 13 ALU fns)
Register-in and Register-out Fields of 3 Bits each Shifter Field of 2 bits to select 1 out of three possibilities:
Auxiliary Field of 4 Bits
Total Bits in μ-instruction
= 7 + 4 + 3 + 3 + 2 + 4 = 23
Register-in and Register-out Fields of 3 Bits each Shifter Field of 2 bits to select 1 out of three possibilities:
Auxiliary Field of 4 Bits
Total Bits in μ-instruction
= 7 + 4 + 3 + 3 + 2 + 4 = 23
Consider the following situation and fill in the blanks:The computer starts the tape moving by issuing a command: the processor then monitors the status of the tape by means of a _____. When the tape is in the correct position, the processor issues a _______.- a)Data input, status, data output command
- b)Data input, status control command
- c)Control, status, data output command
- d)Control, status, data input command
Correct answer is option 'C'. Can you explain this answer?
Consider the following situation and fill in the blanks:
The computer starts the tape moving by issuing a command: the processor then monitors the status of the tape by means of a _____. When the tape is in the correct position, the processor issues a _______.
a)
Data input, status, data output command
b)
Data input, status control command
c)
Control, status, data output command
d)
Control, status, data input command
|
Bijoy Sharma answered |
Control command: A control command is issued to activate the peripheral and to inform it what to do.
Status: A status command is used to test various status conditions in the interface and the peripheral.
Data output command causes the interface to respond by transferring data from the bus into one of its register.
Status: A status command is used to test various status conditions in the interface and the peripheral.
Data output command causes the interface to respond by transferring data from the bus into one of its register.
A hardware interrupt is- a)Also called an internal interrupt
- b)Also called an external interrupt
- c)An I/O interrupt
- d)A clock interrupt
Correct answer is option 'B'. Can you explain this answer?
A hardware interrupt is
a)
Also called an internal interrupt
b)
Also called an external interrupt
c)
An I/O interrupt
d)
A clock interrupt
|
Roshni Kumar answered |
Introduction:
A hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program and transfer control to a specific interrupt handler routine. It allows the hardware device to communicate with the processor, informing it of events that require immediate attention.
Explanation:
A hardware interrupt can be either internal or external, depending on the source of the interrupt. Let's understand each option in detail:
a) Also called an internal interrupt:
- An internal interrupt, also known as a software interrupt, is generated by the CPU itself.
- It is triggered by a special instruction in the program code that causes the CPU to transfer control to a specific interrupt handler routine.
- Internal interrupts are not directly related to hardware devices, so they do not fall under the category of hardware interrupts.
b) Also called an external interrupt:
- An external interrupt is generated by an external hardware device.
- When a hardware device needs to interrupt the normal execution of a program, it sends a signal to the processor, indicating that an interrupt has occurred.
- The processor then transfers control to the corresponding interrupt handler routine to handle the event.
- External interrupts are directly related to hardware devices and are commonly used for input/output operations, such as keyboard input, mouse input, etc.
c) An I/O interrupt:
- An I/O interrupt is a specific type of hardware interrupt that is generated by input/output devices.
- When an input/output device, such as a disk drive or a network card, completes a task or encounters an error, it can generate an I/O interrupt to inform the processor.
- The processor then interrupts the current program execution and transfers control to the appropriate interrupt handler routine to handle the I/O operation.
d) A clock interrupt:
- A clock interrupt is a specific type of hardware interrupt generated by the system clock or a timer device.
- It is used to keep track of time and schedule tasks.
- The clock interrupt occurs at regular intervals and is used by the operating system to perform various time-related operations, such as updating the system time, scheduling tasks, etc.
Conclusion:
In conclusion, a hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program. An external interrupt, also known as a hardware interrupt, is triggered by an external hardware device and is used for input/output operations. Therefore, the correct answer is option 'B' - Also called an external interrupt.
A hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program and transfer control to a specific interrupt handler routine. It allows the hardware device to communicate with the processor, informing it of events that require immediate attention.
Explanation:
A hardware interrupt can be either internal or external, depending on the source of the interrupt. Let's understand each option in detail:
a) Also called an internal interrupt:
- An internal interrupt, also known as a software interrupt, is generated by the CPU itself.
- It is triggered by a special instruction in the program code that causes the CPU to transfer control to a specific interrupt handler routine.
- Internal interrupts are not directly related to hardware devices, so they do not fall under the category of hardware interrupts.
b) Also called an external interrupt:
- An external interrupt is generated by an external hardware device.
- When a hardware device needs to interrupt the normal execution of a program, it sends a signal to the processor, indicating that an interrupt has occurred.
- The processor then transfers control to the corresponding interrupt handler routine to handle the event.
- External interrupts are directly related to hardware devices and are commonly used for input/output operations, such as keyboard input, mouse input, etc.
c) An I/O interrupt:
- An I/O interrupt is a specific type of hardware interrupt that is generated by input/output devices.
- When an input/output device, such as a disk drive or a network card, completes a task or encounters an error, it can generate an I/O interrupt to inform the processor.
- The processor then interrupts the current program execution and transfers control to the appropriate interrupt handler routine to handle the I/O operation.
d) A clock interrupt:
- A clock interrupt is a specific type of hardware interrupt generated by the system clock or a timer device.
- It is used to keep track of time and schedule tasks.
- The clock interrupt occurs at regular intervals and is used by the operating system to perform various time-related operations, such as updating the system time, scheduling tasks, etc.
Conclusion:
In conclusion, a hardware interrupt is a signal generated by a hardware device to interrupt the normal execution of a program. An external interrupt, also known as a hardware interrupt, is triggered by an external hardware device and is used for input/output operations. Therefore, the correct answer is option 'B' - Also called an external interrupt.
A CPU has a cache with block size 64 bytes. The main memory has k blocks, each block being c bytes wide. Consecutive c-byte chunks are mapped on consecutive blocks with warp-around. All the k blocks can be accessed in parallel, but two accesses to the same block must be serialized. A cache block access may involve multiple iterations of parallel block accesses depending on the amount of data obtained by accessing all the k-blocks in parallel. Each iteration requires decoding the block numbers to be accessed in parallel and this takes k/2 ns.
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is- a)92 ns
- b)104 ns
- c)172 ns
- d)184 ns
Correct answer is option 'D'. Can you explain this answer?
A CPU has a cache with block size 64 bytes. The main memory has k blocks, each block being c bytes wide. Consecutive c-byte chunks are mapped on consecutive blocks with warp-around. All the k blocks can be accessed in parallel, but two accesses to the same block must be serialized. A cache block access may involve multiple iterations of parallel block accesses depending on the amount of data obtained by accessing all the k-blocks in parallel. Each iteration requires decoding the block numbers to be accessed in parallel and this takes k/2 ns.
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is
The latency of one block access is 80 ns. If c = 2 and k = 24, then latency of retrieving a cache block starting at address zero from main memory is
a)
92 ns
b)
104 ns
c)
172 ns
d)
184 ns
|
Kajal Sharma answered |
Cache block size = 64 bytes
Main memory has K banks or k = 24
Each bank is 2 byte long because c = 2
Total time for one parallel access
Total latency time = CT
= 2 x 92 = 184 ns
Main memory has K banks or k = 24
Each bank is 2 byte long because c = 2
Total time for one parallel access
Total latency time = CT
= 2 x 92 = 184 ns
______ is a piece of hardware that executes a set of machine-language instructions.- a)Controller
- b)Bus
- c)Processor
- d)Motherboard
Correct answer is option 'C'. Can you explain this answer?
______ is a piece of hardware that executes a set of machine-language instructions.
a)
Controller
b)
Bus
c)
Processor
d)
Motherboard
|
Ipsita Dasgupta answered |
Processor or processing unit is an electronic CKT which perform operations on some external source, usually memory or some data stream. Processor executes a set of machine language instructions.
To prevent signals, from colliding on the bus, _______ prioritize access to memory by I/O channels and processors.- a)A register
- b)Interrupts '
- c)The processor scheduler
- d)A controller
Correct answer is option 'D'. Can you explain this answer?
To prevent signals, from colliding on the bus, _______ prioritize access to memory by I/O channels and processors.
a)
A register
b)
Interrupts '
c)
The processor scheduler
d)
A controller
|
Megha Dasgupta answered |
To prevent signals from colliding on the bus, a controller prioritize access to memory by I/O channels and processors.
The disadvantage of hard-wired control units with flip-flops is ______.- a)Design becomes complex
- b)It require more number of flip-flops
- c)Control circuit speed does not matches with flip-flops
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
The disadvantage of hard-wired control units with flip-flops is ______.
a)
Design becomes complex
b)
It require more number of flip-flops
c)
Control circuit speed does not matches with flip-flops
d)
None of these
|
|
Meghana Rane answered |
The disadvantage of hardwired control units with flip-flops is that it requires more number of flip- flops.
A microprogrammed control unit- a)Is faster than a hard-wired control unit.
- b)Facilitates easy implementation of new instructions.
- c)Is useful when very small programs are to be run.
- d)Usually refers to the control unit of a microprocessor.
Correct answer is option 'B'. Can you explain this answer?
A microprogrammed control unit
a)
Is faster than a hard-wired control unit.
b)
Facilitates easy implementation of new instructions.
c)
Is useful when very small programs are to be run.
d)
Usually refers to the control unit of a microprocessor.
|
|
Dishani Bajaj answered |
A micro-programmed control unit facilitates easy implementation of new instructions than hardwired.
A bi-directional bus between a memory and CPU, possibly has three states. While the bus behaves like a open circuit, the output does not carry a signal in other state it carry signal in both'direction. Which one of the following is 3rd state?- a)0
- b)1
- c)High impedance
- d)(a) and (c) both
Correct answer is option 'C'. Can you explain this answer?
A bi-directional bus between a memory and CPU, possibly has three states. While the bus behaves like a open circuit, the output does not carry a signal in other state it carry signal in both'direction. Which one of the following is 3rd state?
a)
0
b)
1
c)
High impedance
d)
(a) and (c) both
|
|
Maulik Pillai answered |
Three states of bi-directional bus is input data to RAM, output data to RAM and high impedance.
_______ improve system performance by temporarily storing data during transfers between devices or processes that operate at different speeds.- a)Caches
- b)Controllers
- c)Buffers
- d)Registers
Correct answer is option 'C'. Can you explain this answer?
_______ improve system performance by temporarily storing data during transfers between devices or processes that operate at different speeds.
a)
Caches
b)
Controllers
c)
Buffers
d)
Registers
|
Kunal Sen answered |
Buffers is a data area shared by hardware devices or program processes that operate at different speeds or with different sent of priorities.
Following are some statements associated with microprocessors. Identify the false statement.- a)The control unit is the component of the CPU that implements the microprocessors instruction set.
- b)The instruction received by the CPU is decoded by the arithmetic logic unit.
- c)A CPU register is used to hold a binary value temporarily for storage, for manipulation, and/ or for simple calculations.
- d)The control units are programmed and not hardwired.
Correct answer is option 'B'. Can you explain this answer?
Following are some statements associated with microprocessors. Identify the false statement.
a)
The control unit is the component of the CPU that implements the microprocessors instruction set.
b)
The instruction received by the CPU is decoded by the arithmetic logic unit.
c)
A CPU register is used to hold a binary value temporarily for storage, for manipulation, and/ or for simple calculations.
d)
The control units are programmed and not hardwired.
|
Anmol Basu answered |
False Statement: The instruction received by the CPU is decoded by the arithmetic logic unit.
Explanation:
The arithmetic logic unit (ALU) is responsible for performing arithmetic and logical operations on the data stored in the CPU registers. It is a component of the CPU, but it does not decode instructions.
Let's break down the given statements and explain each one in detail:
a) The control unit is the component of the CPU that implements the microprocessor's instruction set.
- The control unit is responsible for managing and coordinating the activities of the CPU. It fetches instructions from memory, decodes them, and controls the operations of other components, such as ALU and registers, to execute the instructions.
b) The instruction received by the CPU is decoded by the arithmetic logic unit.
- This statement is false. The ALU does not decode instructions. It performs arithmetic and logical operations on the data, but the instruction decoding is the responsibility of the control unit.
c) A CPU register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations.
- CPU registers are small, fast storage locations within the CPU. They are used to store data temporarily during processing. Registers are used for various purposes, including holding operands, intermediate results, and memory addresses.
d) The control units are programmed and not hardwired.
- This statement is true. The control unit is typically implemented using logic circuits, which can be programmed using microcode or firmware. The control unit interprets instructions and generates the appropriate control signals to manage the flow of data and control the operations of other CPU components.
In summary, the false statement is option 'b' because the instruction decoding is not performed by the arithmetic logic unit (ALU).
Explanation:
The arithmetic logic unit (ALU) is responsible for performing arithmetic and logical operations on the data stored in the CPU registers. It is a component of the CPU, but it does not decode instructions.
Let's break down the given statements and explain each one in detail:
a) The control unit is the component of the CPU that implements the microprocessor's instruction set.
- The control unit is responsible for managing and coordinating the activities of the CPU. It fetches instructions from memory, decodes them, and controls the operations of other components, such as ALU and registers, to execute the instructions.
b) The instruction received by the CPU is decoded by the arithmetic logic unit.
- This statement is false. The ALU does not decode instructions. It performs arithmetic and logical operations on the data, but the instruction decoding is the responsibility of the control unit.
c) A CPU register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations.
- CPU registers are small, fast storage locations within the CPU. They are used to store data temporarily during processing. Registers are used for various purposes, including holding operands, intermediate results, and memory addresses.
d) The control units are programmed and not hardwired.
- This statement is true. The control unit is typically implemented using logic circuits, which can be programmed using microcode or firmware. The control unit interprets instructions and generates the appropriate control signals to manage the flow of data and control the operations of other CPU components.
In summary, the false statement is option 'b' because the instruction decoding is not performed by the arithmetic logic unit (ALU).
Horizontal microinstruction have which of the following attributes?
1. Short formats
2. Limited ability to express parallel micro operations.
3. Considerable encoding of the control information;- a)1 and 2
- b)2 and 3
- c)1,2 and 3
- d)None of these
Correct answer is option 'D'. Can you explain this answer?
Horizontal microinstruction have which of the following attributes?
1. Short formats
2. Limited ability to express parallel micro operations.
3. Considerable encoding of the control information;
1. Short formats
2. Limited ability to express parallel micro operations.
3. Considerable encoding of the control information;
a)
1 and 2
b)
2 and 3
c)
1,2 and 3
d)
None of these
|
|
Madhurima Chakraborty answered |
Horizontal micro instructions have following attributes:
1. Long formats.
2. Ability to express a high degree of parallelism .
3 . Little encoding of the control information.
1. Long formats.
2. Ability to express a high degree of parallelism .
3 . Little encoding of the control information.
The following are four statements regarding what a CPU with only a set of 32 bit registers can perform.
1. Hold and operate on 32 bit integers.
2. Hold and operate on 16 bit integers.
3. Hold and operate on 64 bit floating point arithmetic.
4. Hold and operate on 16 bit UNICODE characters.Which of the following is true about such a CPU?- a)1, 2 and 3 only
- b)1, 3 and 4 only
- c)1, 2 and 4 only
- d) All are true
Correct answer is option 'C'. Can you explain this answer?
The following are four statements regarding what a CPU with only a set of 32 bit registers can perform.
1. Hold and operate on 32 bit integers.
2. Hold and operate on 16 bit integers.
3. Hold and operate on 64 bit floating point arithmetic.
4. Hold and operate on 16 bit UNICODE characters.
1. Hold and operate on 32 bit integers.
2. Hold and operate on 16 bit integers.
3. Hold and operate on 64 bit floating point arithmetic.
4. Hold and operate on 16 bit UNICODE characters.
Which of the following is true about such a CPU?
a)
1, 2 and 3 only
b)
1, 3 and 4 only
c)
1, 2 and 4 only
d)
All are true
|
|
Subhankar Shah answered |
A CPU with only a set of 32 bit registers can perform:
1. Hold and operate on 32 bit integers.
2. Hold and operate on 16 bits integers.
3. Hold and operate on 16 bits Unicode characters.
1. Hold and operate on 32 bit integers.
2. Hold and operate on 16 bits integers.
3. Hold and operate on 16 bits Unicode characters.
The system bus is made up of- a)Data bus
- b)Data bus and address bus
- c)Data bus and control bus
- d)Data bus, control bus and address bus
Correct answer is option 'D'. Can you explain this answer?
The system bus is made up of
a)
Data bus
b)
Data bus and address bus
c)
Data bus and control bus
d)
Data bus, control bus and address bus
|
|
Anshu Mehta answered |
System bus is a single computer bus that connects the major components of a computer system, combining the function of a data bus to carry information, an address bus to determine where it should be sent and a control bus to determine its operation.
Consider an unpipelined processor assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operation and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock, ignore any latency impact.Q. What is the average instruction execution time for unpipelined processor?- a)3.4 ns
- b)4.4 ns
- c)3.1 ns
- d)1.2 ns
Correct answer is option 'B'. Can you explain this answer?
Consider an unpipelined processor assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operation and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock, ignore any latency impact.
Q. What is the average instruction execution time for unpipelined processor?
a)
3.4 ns
b)
4.4 ns
c)
3.1 ns
d)
1.2 ns
|
|
Tanvi Datta answered |
Average instruction execution time
Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transm itted, way of achieving this ______.- a)is by means of a strobe pulse from one of the unit
- b)Is by means of handshaking
- c)Both (a) and (b)
- d)None of these
Correct answer is option 'C'. Can you explain this answer?
Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transm itted, way of achieving this ______.
a)
is by means of a strobe pulse from one of the unit
b)
Is by means of handshaking
c)
Both (a) and (b)
d)
None of these
|
|
Arnab Kapoor answered |
A synchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted.
Two way of achieving this:
1. By means of a strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur.
2. To accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. This type of agreement between two independent units is referred to as handshaking.
Two way of achieving this:
1. By means of a strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur.
2. To accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. This type of agreement between two independent units is referred to as handshaking.
Halt operation comes under ________ .- a)Data transfer
- b)Control transfer
- c)Conversion
- d)I/O transfer
Correct answer is option 'B'. Can you explain this answer?
Halt operation comes under ________ .
a)
Data transfer
b)
Control transfer
c)
Conversion
d)
I/O transfer
|
|
Ipsita Dasgupta answered |
Halt operation comes under control transfer.
The following are four statements about Reduced Instruction Set Computer (RISC) architectures.
1. The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.
2. No arithmetic or logical instruction can refer to the memory directly.
3. A comparatively large number of user registers are available.
4. Instructions can be easily decoded through hard-wired control units.Which of the above statements is true?- a)1 and 3 only
- b)1,3 and 4 only
- c)1, 2 and 3 only
- d)All of these
Correct answer is option 'D'. Can you explain this answer?
The following are four statements about Reduced Instruction Set Computer (RISC) architectures.
1. The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.
2. No arithmetic or logical instruction can refer to the memory directly.
3. A comparatively large number of user registers are available.
4. Instructions can be easily decoded through hard-wired control units.
1. The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.
2. No arithmetic or logical instruction can refer to the memory directly.
3. A comparatively large number of user registers are available.
4. Instructions can be easily decoded through hard-wired control units.
Which of the above statements is true?
a)
1 and 3 only
b)
1,3 and 4 only
c)
1, 2 and 3 only
d)
All of these
|
Janani Joshi answered |
Reduced instruction set uses comparatively large number of user registers, all arithmetic or logical instruction refer to memory via registers only, instructions can be easily decoded through hardwired control unit and is small instruction set and is usually a subject of a CISI instruction set
Consider an unpipelined processor assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operation and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock, ignore any latency impact.Q. What speedup gain after pipelined the processor? - a)3.4 ns
- b)3.8 ns
- c)3.7 ns
- d)1.2 ns
Correct answer is option 'C'. Can you explain this answer?
Consider an unpipelined processor assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operation and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock, ignore any latency impact.
Q. What speedup gain after pipelined the processor?
a)
3.4 ns
b)
3.8 ns
c)
3.7 ns
d)
1.2 ns
|
Tanishq Malik answered |
Average instruction time pipelined = 1 + 0.2 = 1.2 ns
Speedup from pipelined
Speedup from pipelined
In Flynn’s classification of computers, the vector and array classes of machines belong to- a)Single instruction/single data category
- b)Single instruction/multiple data category
- c)Multiple instruction/single data category
- d)Multiple instruction/multiple data category
Correct answer is option 'B'. Can you explain this answer?
In Flynn’s classification of computers, the vector and array classes of machines belong to
a)
Single instruction/single data category
b)
Single instruction/multiple data category
c)
Multiple instruction/single data category
d)
Multiple instruction/multiple data category
|
Khan Jasim answered |
Arrays use single intruction and multiple data category(SIMD)
The following are the some of the sequences of operations in instruction cycle, which one is correct sequence?- a)
- b)
- c)
- d) None of these
Correct answer is option 'A'. Can you explain this answer?
The following are the some of the sequences of operations in instruction cycle, which one is correct sequence?
a)
b)
c)
d)
None of these
|
|
Isha Deshpande answered |
1. PC → MAR
2. M[MAR] → MDR
PC + 1 → PC
3. M[MDR] → IR
Represents the instruction fetch cycle
2. M[MAR] → MDR
PC + 1 → PC
3. M[MDR] → IR
Represents the instruction fetch cycle
Consider the following figure:
The above circuit represents____.
1. Hard-wired control unit
2. Micro programmed control unit- a)Only 1
- b)Only 2
- c) Both 1 and 2
- d)Either 1 or 2
Correct answer is option 'C'. Can you explain this answer?
Consider the following figure:
The above circuit represents____.
1. Hard-wired control unit
2. Micro programmed control unit
The above circuit represents____.
1. Hard-wired control unit
2. Micro programmed control unit
a)
Only 1
b)
Only 2
c)
Both 1 and 2
d)
Either 1 or 2
|
|
Arka Bajaj answered |
Since PLA is neither a hard-wired model nor a memory.
∴ We can say control unit with PLA as Hardwired or micro programmed control unit.
∴ We can say control unit with PLA as Hardwired or micro programmed control unit.
Which set of instruction transfers the memory word specified by the effective address to AC or Load to AC?- a)
- b)
- c)
- d)
Correct answer is option 'B'. Can you explain this answer?
Which set of instruction transfers the memory word specified by the effective address to AC or Load to AC?
a)
b)
c)
d)
|
|
Subhankar Goyal answered |
LDA AC load to AC instruction transfers the memory word specified by the effective address to AC
Here register MD represent MDR.
Here register MD represent MDR.
Chapter doubts & questions for Control Unit - Computer Architecture & Organisation (CAO) 2025 is part of Computer Science Engineering (CSE) exam preparation. The chapters have been prepared according to the Computer Science Engineering (CSE) exam syllabus. The Chapter doubts & questions, notes, tests & MCQs are made for Computer Science Engineering (CSE) 2025 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests here.
Chapter doubts & questions of Control Unit - Computer Architecture & Organisation (CAO) in English & Hindi are available as part of Computer Science Engineering (CSE) exam.
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Computer Architecture & Organisation (CAO)
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