Maskable Interrupts

Maskable interrupts are those interrupts that can be temporarily ignored by the system. The CPU can decide whether to handle them or not based on the current system state. Here are some key points to know about maskable interrupts:

- These interrupts can be enabled or disabled by software.
- When an interrupt occurs, the CPU checks the status of the interrupt mask to decide whether to handle the interrupt or not.
- If the mask bit is set, the interrupt is ignored and the CPU continues executing the current instruction.
- If the mask bit is clear, the CPU pauses its current task and handles the interrupt.

Examples of maskable interrupts include keyboard input, mouse input, and disk I/O operations.

Non-Maskable Interrupts

Non-maskable interrupts (NMIs) are those interrupts that cannot be ignored by the system. These are typically reserved for critical events that require immediate attention from the CPU. Some key points to know about NMIs include:

- These interrupts cannot be disabled by software.
- When an NMI occurs, it takes priority over all other interrupts and the CPU immediately stops executing its current task to handle the interrupt.
- NMIs are typically used for events such as power failures, hardware faults, and software errors.

Vectored Interrupts

Vectored interrupts are a type of interrupt that provides additional information to the CPU about the source of the interrupt. Rather than simply indicating that an interrupt has occurred, vectored interrupts provide a specific memory address that corresponds to the interrupt handler routine. This allows the CPU to quickly and efficiently handle the interrupt without having to search for the corresponding handler routine.

High Priority Interrupts

High priority interrupts are those interrupts that are given priority over other interrupts in the system. These interrupts are typically used for critical events that require immediate attention, such as system errors or hardware faults. When a high priority interrupt occurs, the CPU immediately pauses its current task and handles the interrupt. Other interrupts that occur during this time are queued and handled once the high priority interrupt has been resolved.