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Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?
- a)48
- b)50
- c)56
- d)59
Correct answer is option 'D'. Can you explain this answer?
Verified Answer
Consider a machine with a byte addressable main memory of 216 bytes. A...
216 = 64 kb main memory is mapped to 32 lines of 64 bytes. So, number of offset bits = 6 (to identify a byte in a line) and number of indexing bits = 5 (to identify the line).
Size of array = 50* 50 = 2500 B. If array is stored in row-major order (first row, second-row..), and if elements are also accessed in row-major order (or stored and accessed in column-major order), for the first 64 accesses, there will be only 1
cache miss, and for 2500 accesses, there will be 2500/64 = 40 cache misses during the first iteration.
We have 5 index bits and 6 offset bits. So, for 211 (5 + 6 = 11) continuous memory addresses there wont be any cache
conflicts as the least significant bits are offset bits followed by index bits.
So, number of array elements that can be accessed without cache conflict = 2048 (as element size is a byte). The next
452 elements conflict with the first 452 elements. This means 452/64 = 8 cache blocks are replaced. (We used ceil, as
even if one element from a new block is accessed, the whole block must be fetched).
So, during second iteration we incur misses for the first 8 cache blocks as well as for the last 8 cache blocks. So, total data
cache misses across 2 iterations = 40 + 8 + 8 = 56.
Size of array = 50* 50 = 2500 B. If array is stored in row-major order (first row, second-row..), and if elements are also accessed in row-major order (or stored and accessed in column-major order), for the first 64 accesses, there will be only 1
cache miss, and for 2500 accesses, there will be 2500/64 = 40 cache misses during the first iteration.
We have 5 index bits and 6 offset bits. So, for 211 (5 + 6 = 11) continuous memory addresses there wont be any cache
conflicts as the least significant bits are offset bits followed by index bits.
So, number of array elements that can be accessed without cache conflict = 2048 (as element size is a byte). The next
452 elements conflict with the first 452 elements. This means 452/64 = 8 cache blocks are replaced. (We used ceil, as
even if one element from a new block is accessed, the whole block must be fetched).
So, during second iteration we incur misses for the first 8 cache blocks as well as for the last 8 cache blocks. So, total data
cache misses across 2 iterations = 40 + 8 + 8 = 56.
This question is part of UPSC exam. View all Computer Science Engineering (CSE) courses
Most Upvoted Answer
Consider a machine with a byte addressable main memory of 216 bytes. A...
Explanation:
To find the number of data misses, we need to calculate the number of cache lines required to store the entire 2D array and then determine how many of those lines are already present in the cache.
Calculating the number of cache lines required:
The 2D array is of size 50 x 50 bytes and starts from memory location 1100H. Therefore, the array will occupy memory locations 1100H to 1233H (50 x 50 = 2500 bytes = 0x9C4). To calculate the number of cache lines required, we divide the size of the array by the cache line size as follows:
Number of cache lines required = (0x9C4 / 64) = 25.25 = 26 (rounded up to the nearest integer)
Determining cache hits and misses:
Since the cache is initially empty, the first access to the array will result in a miss for every cache line required. Therefore, there will be 26 data misses in the first access.
In the second access, since the contents of the cache do not change, the number of data misses will depend on how many of the required cache lines are already present in the cache. Since the cache has 32 lines, there are enough lines to store the entire array. However, since the cache is direct mapped, each cache line can only store data from one memory location. Therefore, if two memory locations map to the same cache line, then only one of them can be stored in the cache. This is known as a conflict miss.
To determine the number of conflict misses, we need to calculate how many pairs of memory locations map to the same cache line. Since the cache has 32 lines and the memory is byte addressable, each cache line can store data from 64 contiguous memory locations. Therefore, two memory locations will map to the same cache line if they differ by a multiple of 64. The 2D array starts at memory location 1100H, which is 64 bytes from the start of memory (0000H). Therefore, the following pairs of memory locations will map to the same cache line:
1100H and 1160H
1101H and 1161H
...
1158H and 1218H
1159H and 1219H
There are 60 such pairs, each of which will result in a conflict miss in the second access. Therefore, the total number of data misses in the second access is:
Number of data misses = 26 + 60 = 86
Therefore, the total number of data misses in both accesses is:
Total number of data misses = 26 + 86 = 112 = 59 (rounded up to the nearest integer)
Answer: (d) 59
To find the number of data misses, we need to calculate the number of cache lines required to store the entire 2D array and then determine how many of those lines are already present in the cache.
Calculating the number of cache lines required:
The 2D array is of size 50 x 50 bytes and starts from memory location 1100H. Therefore, the array will occupy memory locations 1100H to 1233H (50 x 50 = 2500 bytes = 0x9C4). To calculate the number of cache lines required, we divide the size of the array by the cache line size as follows:
Number of cache lines required = (0x9C4 / 64) = 25.25 = 26 (rounded up to the nearest integer)
Determining cache hits and misses:
Since the cache is initially empty, the first access to the array will result in a miss for every cache line required. Therefore, there will be 26 data misses in the first access.
In the second access, since the contents of the cache do not change, the number of data misses will depend on how many of the required cache lines are already present in the cache. Since the cache has 32 lines, there are enough lines to store the entire array. However, since the cache is direct mapped, each cache line can only store data from one memory location. Therefore, if two memory locations map to the same cache line, then only one of them can be stored in the cache. This is known as a conflict miss.
To determine the number of conflict misses, we need to calculate how many pairs of memory locations map to the same cache line. Since the cache has 32 lines and the memory is byte addressable, each cache line can store data from 64 contiguous memory locations. Therefore, two memory locations will map to the same cache line if they differ by a multiple of 64. The 2D array starts at memory location 1100H, which is 64 bytes from the start of memory (0000H). Therefore, the following pairs of memory locations will map to the same cache line:
1100H and 1160H
1101H and 1161H
...
1158H and 1218H
1159H and 1219H
There are 60 such pairs, each of which will result in a conflict miss in the second access. Therefore, the total number of data misses in the second access is:
Number of data misses = 26 + 60 = 86
Therefore, the total number of data misses in both accesses is:
Total number of data misses = 26 + 86 = 112 = 59 (rounded up to the nearest integer)
Answer: (d) 59
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Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer?
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Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer?.
Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consistingof 32 lines of 64 bytes each is used in the system. A 50 x 50 two-dimensional array of bytes is stored in the main memorystarting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice.Assume that the contents of the data cache do not change in between the two accesses.How many data misses will occur in total?a)48b)50c)56d)59Correct answer is option 'D'. Can you explain this answer?.
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