A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; iandlt;512; i++){for (j=0; jandlt;512; j++){x +=A[i] [j];}}P2:for (i=0; iandlt;512; i++){for (j=0; jandlt;512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? - EduRev Computer Science Engineering (CSE) Question

Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity

Open App

Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > A CPU has a 32 KB direct mapped cache with 12...

Join the Discussion on the App

A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.
P1:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[i] [j];
}
}
P2:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[j] [i];
}
}
P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in
registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.
The value of the ratio

a)
0
b)
1/16
c)
1/8
d)
16

Correct answer is option 'B'. Can you explain this answer?

FREE This question is part of

Test: Cache Memory- 1

Attempt Test

Attempt this Test

Verified Answer

A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppos...

Number of Cache Lines

In 1 Cache Line

P₁

P₂

It is so because for
P₁ for every line there is a miss, and once a miss is processed we get 16 elements in memory. So another miss happens after 16 elements.
for
P₂ for every element there is a miss coz storage is row major order(by default) and we are accessing column wise.
Hence, answer = option B

View all questions of this test

View all answers Start learning for free

< Previous Question Next Question >

Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of M1 is

View answer

In a C program, an array is declared as float A[2048]. Each array element is 4 Bytes in size, and the starting address of the array is 0x00000000. This program is run on a computer that has a direct mapped data cache of size 8 Kbytes, with block (lin e) size of 16 Bytes.a. Which elements of the array conflict with element A[0] in the data cache? Justify your answer briefly.b. If the program accesses the elements of this array one by one in reverse order i.e., starting with the last element and ending with the first element, how many data cache misses would occur? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered. Correct answer is '(

View answer

Consider a two dimensional array A[1…10][3….8] that is column index ranges from 3 to 8 and row index ranges from 1 to 10. Now suppose element are arranged in column major order. If base address of A is 1000 then address of element A[5][7] will be _________ (Assume size of each element is 1). Correct answer is '1044'. Can you explain this answer?

View answer

Example 1:Consider array has 4 elements and a searching element 16.A[4]= {10, 16, 22, 25}The number of iterations are required to search an element by using a binary search= T1Example 2:Consider array has 4 elements and a searching element 22.A[4]= {10, 16, 22, 25}The number of iterations are required to search an element by using a binary search= T2Note: Searching is successful.Q.Which of the following statement are true?

View answer

Example 1:Consider array has 4 elements and a searching element 16.A[4]= {10, 16, 22, 25}The number of iterations are required to search an element by using a binary search= T1Example 2:Consider array has 4 elements and a searching element 22.A[4]= {10, 16, 22, 25}The number of iterations are required to search an element by using a binary search= T2Note: Searching is successful.Which of the following statement are true?

View answer

Top Courses for Computer Science Engineering (CSE)View all

GATE Computer Science Engineering(CSE) 2025 Mock Test Series

Question Bank for GATE Computer Science Engineering

General Aptitude for GATE

Computer Networks

Programming and Data Structures

Top Courses for Computer Science Engineering (CSE)

View all

A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer?

Share with a Friend

Answer this doubt

Question Description
A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer?.

Solutions for A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.

Here you can find the meaning of A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer?, a detailed solution for A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? has been provided alongside types of A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice A CPU has a 32 KB direct mapped cache with 128 byte-block size. Suppose A is two dimensional array of size with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.P1:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[i] [j];}}P2:for (i=0; i<512; i++){for (j=0; j<512; j++){x +=A[j] [i];}}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are inregisters. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.The value of the ratio a)0b)1/16c)1/8d)16Correct answer is option 'B'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.

Explore Courses for Computer Science Engineering (CSE) exam