Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? - EduRev Computer Science Engineering (CSE) Question

Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity

Open App

Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > Consider the following circuit with initial s...

Join the Discussion on the App

Consider the following circuit with initial state

The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C. The clock period of

nanosecond. Which one is the correct plot of Y?

Correct answer is option 'A'. Can you explain this answer?

FREE This question is part of

Test: Circuit Outputs

Attempt Test

Attempt this Test

Verified Answer

Consider the following circuit with initial stateThe D Flip-flops are ...

Given clock is + edge triggered.
See the first positive edge. X is 0, and hence output is 0. Q₀ is 1 and Q₀' is 0.
Second + edge, X is 1 and Q0' is also one. So, output is 1. (When second positive edge of the clock arrives, Q₀' would surely be 1 because the set up time of flip flop is given as 20 ns and the clock period is >= 40 ns)
Third + edge, X is 1 and Q₀' is 0, So, output is 0. (Q₀' becomes 0 before the 3rd positive edge, but output Y won't change as the flip flop is positive edge triggered)
Now, output never changes back to 1 as Q₀' is always 0 and when Q₀' finally becomes 1, X is 0.
Set up time and hold times are given just to ensure that edge triggering work properly.

View all questions of this test

View all answers Start learning for free

< Previous Question Next Question >

Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

Consider the following circuitThe flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0Q1 Let the initial state be 00. The state transition sequence is

View answer

Consider the following circuit involving a positive edge triggered D FF.Consider the following. represents the logic level on the line a in the i-th clock period. represent the compliment of A. The correct output sequence on A over the clock periods 1through is

View answer

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

View answer

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

View answer

The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is __________.

View answer

Top Courses for Computer Science Engineering (CSE)View all

GATE Computer Science Engineering(CSE) 2025 Mock Test Series

Question Bank for GATE Computer Science Engineering

General Aptitude for GATE

Computer Networks

Programming and Data Structures

Top Courses for Computer Science Engineering (CSE)

View all

Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer?

Share with a Friend

Answer this doubt

Question Description
Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer?.

Solutions for Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.

Here you can find the meaning of Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer?, a detailed solution for Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? has been provided alongside types of Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice Consider the following circuit with initial stateThe D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the correct plot of Y?a)b)c)d)Correct answer is option 'A'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.

Explore Courses for Computer Science Engineering (CSE) exam