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A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?
- a)2
- b)4
- c)8
- d)16
Correct answer is option 'C'. Can you explain this answer?
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Verified Answer
A computer uses 46–bit virtual address, 32–bit physical ad...
Let the page size is of 'x' bits
Size of T1 = 2 ^ x bytes
(This is because T1 occupies exactly one page)
Now, number of entries in T1 = (2^x) / 4
(This is because each page table entry is 32 bits or 4 bytes in size)
Number of entries in T1 = Number of second level page tables
(Because each I-level page table entry stores the base address of page of II-level page table)
Total size of second level page tables = ((2^x) / 4) * (2^x)
Similarly, number of entries in II-level page tables = Number of III level page tables = ((2^x) / 4) * ((2^x) / 4)
Total size of third level page tables = ((2^x) / 4) * ((2^x) / 4) * (2^x)
Similarly, total number of entries (pages) in all III-level
page tables = ((2^x) / 4) * ((2^x) / 4) * ((2^x) / 4)
= 2^(3x - 6)
Size of virtual memory = 2^46 Number of pages in virtual memory = (2^46) / (2^x) = 2^(46 - x)
Total number the pages in the III-level page tables = Number of pages in virtual memory
2^(3x - 6) = 2^(46 - x)
3x - 6 = 46 - x
4x = 52
x = 13
That means, page size is of 13 bits or Page size = 2^13 bytes = 8 KB
Size of T1 = 2 ^ x bytes
(This is because T1 occupies exactly one page)
Now, number of entries in T1 = (2^x) / 4
(This is because each page table entry is 32 bits or 4 bytes in size)
Number of entries in T1 = Number of second level page tables
(Because each I-level page table entry stores the base address of page of II-level page table)
Total size of second level page tables = ((2^x) / 4) * (2^x)
Similarly, number of entries in II-level page tables = Number of III level page tables = ((2^x) / 4) * ((2^x) / 4)
Total size of third level page tables = ((2^x) / 4) * ((2^x) / 4) * (2^x)
Similarly, total number of entries (pages) in all III-level
page tables = ((2^x) / 4) * ((2^x) / 4) * ((2^x) / 4)
= 2^(3x - 6)
Size of virtual memory = 2^46 Number of pages in virtual memory = (2^46) / (2^x) = 2^(46 - x)
Total number the pages in the III-level page tables = Number of pages in virtual memory
2^(3x - 6) = 2^(46 - x)
3x - 6 = 46 - x
4x = 52
x = 13
That means, page size is of 13 bits or Page size = 2^13 bytes = 8 KB
Most Upvoted Answer
A computer uses 46–bit virtual address, 32–bit physical ad...
Given:
- 46-bit virtual address
- 32-bit physical address
- Three-level paged page table organization
- Page table base register stores the base address of T1
- T1 occupies exactly one page
- Each entry of T1 stores the base address of a page of T2
- Each entry of T2 stores the base address of a page of T3
- Each entry of T3 stores a PTE (32 bits)
- Processor has a 1 MB 16 way set associative virtually indexed physically tagged cache
- Cache block size is 64 bytes
To find: Size of a page in KB
Approach:
1. Calculate the size of the three-level page table.
2. Calculate the number of pages required for the page table.
3. Calculate the maximum number of pages that can be addressed.
4. Calculate the size of a page.
5. Verify that the page size is compatible with the cache block size.
Solution:
1. Size of the three-level page table:
- Each entry in T1 stores the base address of a page of T2. Therefore, each entry in T1 is 32 bits.
- Each entry in T2 stores the base address of a page of T3. Therefore, each entry in T2 is also 32 bits.
- Each entry in T3 stores a PTE (32 bits).
- Therefore, the total size of the page table is:
- Size of T1 = 2^32 bytes (one page)
- Size of T2 = 2^32 * 32 bits = 2^32 * 4 bytes
- Size of T3 = 2^32 * 32 bits * 32 bits = 2^32 * 2^5 * 2^5 bytes = 2^42 bytes
- Total size of the page table = Size of T1 + Size of T2 + Size of T3
= 2^32 + 2^32 * 4 + 2^42 bytes
= 2^32 * 5 + 2^42 bytes
= 5.25 TB
2. Number of pages required for the page table:
- Each page is 2^12 bytes.
- Therefore, the number of pages required for the page table is:
- Number of pages = Total size of the page table / Page size
= 5.25 TB / 2^12 bytes/page
= 2^42 bytes / 2^12 bytes/page
= 2^30 pages
3. Maximum number of pages that can be addressed:
- The virtual address is 46 bits.
- Therefore, the maximum number of pages that can be addressed is:
- Maximum number of pages = 2^46 / 2^12 pages
= 2^34 pages
4. Size of a page:
- Size of a page = Maximum addressable memory / Maximum number of pages
= 2^32 bytes/page
5. Verify compatibility with cache block size:
- The cache block size is 64 bytes.
- Therefore, the page size should be a multiple of 64 bytes.
- Size of a page = 2^32 bytes/page = 4 KB = 64 * 64 bytes
- Therefore, the page size is compatible with the cache block size.
Therefore,
- 46-bit virtual address
- 32-bit physical address
- Three-level paged page table organization
- Page table base register stores the base address of T1
- T1 occupies exactly one page
- Each entry of T1 stores the base address of a page of T2
- Each entry of T2 stores the base address of a page of T3
- Each entry of T3 stores a PTE (32 bits)
- Processor has a 1 MB 16 way set associative virtually indexed physically tagged cache
- Cache block size is 64 bytes
To find: Size of a page in KB
Approach:
1. Calculate the size of the three-level page table.
2. Calculate the number of pages required for the page table.
3. Calculate the maximum number of pages that can be addressed.
4. Calculate the size of a page.
5. Verify that the page size is compatible with the cache block size.
Solution:
1. Size of the three-level page table:
- Each entry in T1 stores the base address of a page of T2. Therefore, each entry in T1 is 32 bits.
- Each entry in T2 stores the base address of a page of T3. Therefore, each entry in T2 is also 32 bits.
- Each entry in T3 stores a PTE (32 bits).
- Therefore, the total size of the page table is:
- Size of T1 = 2^32 bytes (one page)
- Size of T2 = 2^32 * 32 bits = 2^32 * 4 bytes
- Size of T3 = 2^32 * 32 bits * 32 bits = 2^32 * 2^5 * 2^5 bytes = 2^42 bytes
- Total size of the page table = Size of T1 + Size of T2 + Size of T3
= 2^32 + 2^32 * 4 + 2^42 bytes
= 2^32 * 5 + 2^42 bytes
= 5.25 TB
2. Number of pages required for the page table:
- Each page is 2^12 bytes.
- Therefore, the number of pages required for the page table is:
- Number of pages = Total size of the page table / Page size
= 5.25 TB / 2^12 bytes/page
= 2^42 bytes / 2^12 bytes/page
= 2^30 pages
3. Maximum number of pages that can be addressed:
- The virtual address is 46 bits.
- Therefore, the maximum number of pages that can be addressed is:
- Maximum number of pages = 2^46 / 2^12 pages
= 2^34 pages
4. Size of a page:
- Size of a page = Maximum addressable memory / Maximum number of pages
= 2^32 bytes/page
5. Verify compatibility with cache block size:
- The cache block size is 64 bytes.
- Therefore, the page size should be a multiple of 64 bytes.
- Size of a page = 2^32 bytes/page = 4 KB = 64 * 64 bytes
- Therefore, the page size is compatible with the cache block size.
Therefore,
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A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?
Question Description
A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?.
A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?.
Solutions for A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE).
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A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?, a detailed solution for A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? has been provided alongside types of A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? theory, EduRev gives you an
ample number of questions to practice A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
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