Input Capacitance Due to Miller Effect

Miller effect is a phenomenon that occurs in electronic circuits where the input capacitance appears to be increased due to the presence of a large capacitance in the output circuit. In this case, the drain gate capacitance of a junction is assumed to be 2 pF and the common source voltage gain is 20. The input capacitance due to Miller effect can be calculated as follows:

Formula:
Cin = Cdg * (1 + Av)

Where,
Cin = Input capacitance due to Miller effect
Cdg = Drain gate capacitance
Av = Voltage gain

Calculation:
Cin = 2 pF * (1 + 20)
Cin = 42 pF

Explanation:

Miller effect occurs due to the presence of a large capacitance in the output circuit. In this case, the drain gate capacitance of a junction is assumed to be 2 pF. When a voltage signal is applied to the input of the circuit, it is amplified by the common source amplifier. The amplified signal is then passed through the drain gate capacitance to the output circuit.

The drain gate capacitance acts as a feedback capacitor, which causes the input capacitance to appear larger than its actual value. This is because the drain gate capacitance is effectively multiplied by the voltage gain of the circuit.

In this case, the voltage gain is 20, which means that the drain gate capacitance is effectively multiplied by 20. Therefore, the input capacitance due to Miller effect is 42 pF, which is much larger than the actual capacitance of 2 pF.

Conclusion:

Miller effect is a phenomenon that occurs in electronic circuits where the input capacitance appears to be increased due to the presence of a large capacitance in the output circuit. The input capacitance due to Miller effect can be calculated using the formula Cin = Cdg * (1 + Av), where Cdg is the drain gate capacitance and Av is the voltage gain of the circuit. In this case, the input capacitance due to Miller effect is 42 pF, which is much larger than the actual capacitance of 2 pF.